Mode 0; Mode 2 - Philips P89LPC902 User Manual

Philips Semiconductors
TIMERS 0 AND 1
TAMOD - P89LPC901
Address: 8Fh
Not bit addressable
Reset Source(s): Any reset
Reset Value: xxx0xxx0B
BIT SYMBOL
TAMOD.7-1 -
TAMOD.0 T0M2
TnM2-TnM0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure
5-4 shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer
interrupt flag TFn. The count input is enabled to the Timer when TRn = 1. TRn is a control bit in the Special Function Register
TCON (Figure 5-3).
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should
be ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1. See Figure 5-4.
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. See Figure 5-5.

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 5-6. Overflow from TLn
not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn
unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.
2003 Dec 8
7 6
-
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Mode Select bit 2 for Timer 0. Used with T0M1 and T0M0 in the TMOD register to
determine Timer 0 mode (P89LPC901).
Timer Mode
8048 Timer "TLn" serves as 5-bit prescaler. (Mode 0)
16-bit Timer/Counter "THn" and "TLn" are cascaded; there is no prescaler. (Mode 1)
8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it
overflows. (Mode 2)
Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled
by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1
control bits (see text). Timer 1 in this mode is stopped. (Mode 3)
Reserved. User must not configure to this mode.
Reserved. User must not configure to this mode.
PWM mode (see section "Mode 6 - P89LPC901").
Reserved. User must not configure to this mode.
Figure 5-2: Timer/Counter Auxiliary Mode Control register (TAMOD)
5 4
- - -
46
User's Manual - Preliminary -
P89LPC901/902/903
3 2 1
- - -
0
T0M2