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Philips Semiconductors
WATCHDOG TIMER
Table 12-2: P89LPC901/902/903 Watchdog Timeout Values
PRE2-PRE0
WDL in decimal)
000
255
001
255
010
255
011
255
100
255
101
255
110
255
111
255
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
Watchdog
Oscillator
÷32
PCLK
2003 Dec 8
Timeout Period
(in watchdog clock
cycles)
0
33
8,193
0
65
16,385
0
129
32,769
0
257
65,537
0
513
131,073
0
1,025
262,145
0
2,049
524,289
0
4097
1,048,577
PRESCALER
control register
PRE2
PRE1
PRE0
Figure 12-3: Watchdog Timer in Watchdog Mode (WDTE = 1)
Watchdog Clock Source
400KHz Watchdog Oscillator Clock
(Nominal)
82.5µs
20.5ms
162.5µs
41.0ms
322.5µs
81.9ms
642.5µs
163.8ms
.1.28ms
327.7ms
2.56ms
655.4ms
5.12ms
1.31s
10.2ms
2.62s
WDL (C1H)
8-Bit Down
Counter
WDRUN
86
User's Manual - Preliminary -
P89LPC901/902/903
12MHz CCLK (6MHz CCLK/2
Watchdog Clock)
5.50µs
1.37ms
10.8µs
2.73ms
21.5µs
5.46ms
42.8µs
10.9ms
85.5µs
21.8ms
170.8µs
43.7ms
341.5µs
87.4ms
682.8µs
174.8ms
Watchdog reset can also be caused
by an invalid feed sequence, or by
writing to WDCON not immediately
followed by a feed sequence
SHADOW
REGISTER FOR
WDCON
WDTOF
WDCLK
WDCON(A7H)
RESET
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