Philips P89LPC902 User Manual page 24

Philips Semiconductors
GENERAL DESCRIPTION
Name Description
TH0 Timer 0 High
TH1 Timer 1 High
TL0 Timer 0 Low
TL1 Timer 1 Low
TMOD Timer 0 and 1 Mode
TRIM# Internal Oscillator Trim Register
WDCON# Watchdog Control Register
WDL# Watchdog Load
WFEED1# Watchdog Feed 1
WFEED2# Watchdog Feed 2
Notes:
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
- Reserved bits, must be written with 0's.
§ BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is '0'. If any of them is written if BRGEN = 1, result is
unpredictable.
Unimplemented bits in SFRs (labeled '-' ) are X (unknown) at all times. Unless otherwise specified, ones should not be written to
these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are '0's
although they are unknown when read.
1. All ports are in input only (high impendance) state after power-up.
2. The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are
cleared except POF and BOF - the power-on reset value is xx110000.
3. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all 1, WDRUN=1 and WDCLK=1. WDTOF bit is 1 after watchdog
reset and is 0 after power-on reset. Other resets will not affect WDTOF.
4. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization
of the TRIM register.
5. The only reset source that affects these SFRs is power-on reset.
2003 Dec 8
SFR
Address
MSB
8CH
8DH
8AH
8BH
89H - - T1M1
96H - - TRIM.5
A7H PRE2 PRE1 PRE0
C1H
C2H
C3H
24
Bit Functions and Addresses
T1M0 - -
TRIM.4 TRIM.3 TRIM.2
- - WDRUN WDTOF WDCLK
User's Manual - Preliminary -
P89LPC901/902/903
Reset Value
LSB
Hex Binary
00H 00000000
00H 00000000
00H 00000000
00H 00000000
T0M1 T0M0 00H 00000000
TRIM.1 TRIM.0 Notes 4,5
Notes 3,5
FFH 11111111