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Philips P89LPC902 User Manual

8-bit microcontrollers with accelerated two-clock 80c51 core 1kb 3v low-power byte-eraseable flash with 128 byte ram.
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USER
MANUAL
P89LPC901/902/903
8-bit microcontrollers with accelerated two-clock 80C51 core
1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM
Philips
Semiconductors
INTEGRATED CIRCUITS
2003 Dec 8
PHILIPS

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   Summary of Contents for Philips P89LPC902

  • Page 1 USER MANUAL P89LPC901/902/903 8-bit microcontrollers with accelerated two-clock 80C51 core 1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM Philips Semiconductors INTEGRATED CIRCUITS 2003 Dec 8 PHILIPS...
  • Page 2: Table Of Contents

    Pin Descriptions - P89LPC903 ... 15 Special Function Registers ... 16 Special Function Registers Table - P89LPC901 ... 16 Special Function Registers Table - P89LPC902 ... 19 Special Function Registers Table - P89LPC903 ... 22 Memory Organization ... 25 2. Clocks... 27 Enhanced CPU ...
  • Page 3 Philips Semiconductors Table of Contents Mode 6 - P89LPC901 ... 47 Timer Overflow toggle output - P89LPC901 ... 49 6. Real-Time Clock/System Timer... 51 Real-time Clock Source ... 51 Changing RTCS1-0 ... 53 Real-time Clock Interrupt/Wake Up ... 53 Reset Sources Affecting the Real-time Clock... 53 7.
  • Page 4 Philips Semiconductors Table of Contents Feed Sequence ... 84 Watchdog Timer in Timer Mode ... 87 Power down operation ... 87 Watchdog Clock Source ... 87 Periodic wakeup from Power down without an external oscillator ... 89 13. Additional Features... 91 Software Reset ...
  • Page 5 Block Diagram of Oscillator Control - P89LPC901 ......30 Block Diagram of Oscillator Control - P89LPC902 ......31 Block Diagram of Oscillator Control- P89LPC903.
  • Page 6 Keypad Pattern Register - P89LPC902........
  • Page 7: General Description

    Philips Semiconductors GENERAL DESCRIPTION 1. GENERAL DESCRIPTION The P89LPC901/902/903 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC901/902/903 is based on a high performance processor architecture that executes instructions six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC901/902/903 in order to reduce component count, board space, and system cost.
  • Page 8: Product Comparison

    Philips Semiconductors GENERAL DESCRIPTION Logic Symbols KBI4 CIN1A KBI5 CMPREF CLKOUT XTAL2 XTAL1 KBI4 CIN1A KBI5 CMPREF KBI6 CMP1 KBI2 CIN2A KBI0 CMP2 KBI4 CIN1A KBI5 CMPREF KBI2 CIN2A Product comparison The following table highlights differences between these three devices.
  • Page 9 Philips Semiconductors GENERAL DESCRIPTION Block Diagram - P89LPC901 1KB Code Flash Port 3 Configurable I/Os Port 1 Configurable I/Os Port 0 Configurable I/Os Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider Configurable Crystal or Oscillator Resonator 2003 Dec 8...
  • Page 10 Philips Semiconductors GENERAL DESCRIPTION Block Diagram - P89LPC902 1KB Code Flash Port 1 Input Port 0 Configurable I/Os Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider On-Chip Oscillator 2003 Dec 8 High Performance Accelerated 2-clock 80C51 CPU Internal Bus Clock User’s Manual - Preliminary -...
  • Page 11 Philips Semiconductors GENERAL DESCRIPTION Block Diagram - P89LPC903 1KB Code Flash Port 1 Input Port 0 Configurable I/Os Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider On-Chip Oscillator 2003 Dec 8 High Performance Accelerated 2-clock 80C51 CPU Internal Bus Clock User’s Manual - Preliminary -...
  • Page 12: Pin Descriptions - P89lpc901

    Philips Semiconductors GENERAL DESCRIPTION PIN DESCRIPTIONS - P89LPC901 MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.0 - P0.6 6, 7 Port 0: The Keypad Interrupt feature operates with port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below.
  • Page 13 Philips Semiconductors GENERAL DESCRIPTION MNEMONIC PIN NO. TYPE NAME AND FUNCTION XTAL2 Output from the oscillator amplifier (when a crystal oscillator CLKOUTCPU clock divided by 2 when enabled via SFR bit (ENCLK - P3.1 XTAL1 Input to the oscillator circuit and internal clock generator Ground: 0V reference.
  • Page 14: Pin Descriptions - P89lpc902

    Philips Semiconductors GENERAL DESCRIPTION PIN DESCRIPTIONS - P89LPC902 MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.0 - P0.6 2,3,5,6,7 Port 0: The Keypad Interrupt feature operates with port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below.
  • Page 15: Pin Descriptions - P89lpc903

    Philips Semiconductors GENERAL DESCRIPTION PIN DESCRIPTIONS - P89LPC903 MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.0 - P0.6 2,6,7 Port 0: The Keypad Interrupt feature operates with port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below.
  • Page 16: Special Function Registers

    Philips Semiconductors GENERAL DESCRIPTION SPECIAL FUNCTION REGISTERS Note: Special Function Registers (SFRs) accesses are restricted in the following ways: 1. User must NOT attempt to access any SFR locations not defined. 2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
  • Page 17 Philips Semiconductors GENERAL DESCRIPTION Name Description IP0H# Interrupt Priority 0 High IP1*# Interrupt Priority 1 IP1H# Interrupt Priority 1 High KBCON# Keypad Control Register KBMASK# Keypad Interrupt Mask Register KBPATN# Keypad Pattern Register Port 0 Port 1 Port 3 P0M1#...
  • Page 18 Philips Semiconductors GENERAL DESCRIPTION Name Description TCON* Timer 0 and 1 Control Timer 0 High Timer 1 High Timer 0 Low Timer 1 Low TMOD Timer 0 and 1 Mode TRIM# Internal Oscillator Trim Register WDCON# Watchdog Control Register WDL#...
  • Page 19: Special Function Registers Table - P89lpc902

    Philips Semiconductors GENERAL DESCRIPTION Special Function Registers Table - P89LPC902 Name Description ACC* Accumulator AUXR1# Auxiliary Function Register B Register CMP1# Comparator 1 Control Register CMP2# Comparator 2 Control Register DIVM# CPU Clock Divide-by-M Control DPTR Data Pointer (2 bytes)
  • Page 20 Philips Semiconductors GENERAL DESCRIPTION Name Description KBPATN# Keypad Pattern Register Port 0 Port 1 P0M1# Port 0 Output Mode 1 P0M2# Port 0 Output Mode 2 P1M1# Port 1 Output Mode 1 P1M2# Port 1 Output Mode 2 PCON# Power Control Register...
  • Page 21 Philips Semiconductors GENERAL DESCRIPTION Name Description WDCON# Watchdog Control Register WDL# Watchdog Load WFEED1# Watchdog Feed 1 WFEED2# Watchdog Feed 2 2003 Dec 8 Bit Functions and Addresses Address PRE2 PRE1 PRE0 User’s Manual - Preliminary - P89LPC901/902/903 Reset Value...
  • Page 22: Special Function Registers Table - P89lpc903

    Philips Semiconductors GENERAL DESCRIPTION Special Function Registers Table - P89LPC903 Name Description ACC* Accumulator AUXR1# Auxiliary Function Register B Register BRGR0#§ Baud Rate Generator Rate Low BRGR1#§ Baud Rate Generator Rate High BRGCON# Baud Rate Generator Control CMP1# Comparator 1 Control Register...
  • Page 23 Philips Semiconductors GENERAL DESCRIPTION Name Description IP1H# Interrupt Priority 1 High KBCON# Keypad Control Register KBMASK# Keypad Interrupt Mask Register KBPATN# Keypad Pattern Register Port 0 Port 1 P0M1# Port 0 Output Mode 1 P0M2# Port 0 Output Mode 2...
  • Page 24 Philips Semiconductors GENERAL DESCRIPTION Name Description Timer 0 High Timer 1 High Timer 0 Low Timer 1 Low TMOD Timer 0 and 1 Mode TRIM# Internal Oscillator Trim Register WDCON# Watchdog Control Register WDL# Watchdog Load WFEED1# Watchdog Feed 1...
  • Page 25: Memory Organization

    Philips Semiconductors GENERAL DESCRIPTION Memory Organization The P89LPC901/902/903 memory map is shown in Figure 1-1. 03FFh 0300h 02FFh 0200h 01FFh 0100h 00FFh 0000h 1 KB Flash Code Memory Space The various P89LPC901/902/903 memory spaces are as follows: DATA 128 bytes of internal data memory space (00h..7Fh) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC.
  • Page 26 Philips Semiconductors User’s Manual - Preliminary - P89LPC901/902/903 GENERAL DESCRIPTION 2003 Dec 8...
  • Page 27: Clocks

    20 kHz to 12 MHz. The P89LPC902 and P89LPC903 devices allow the user to select between an on-chip watchdog oscillator and an on-chip RC oscillator as the CPU clock source.
  • Page 28: Oscillator Option Selection- P89lpc901

    Philips Semiconductors CLOCKS The oscillator must be configured in one of the following modes: - Low Frequency Crystal - Medium Frequency Crystal - High Frequency Crystal * A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals.
  • Page 29: Watchdog Oscillator Option

    Philips Semiconductors CLOCKS If CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ’1’ to reduce power consumption. On reset, CLKLP is ’0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8MHz or slower.
  • Page 30: Block Diagram Of Oscillator Control - P89lpc901

    Philips Semiconductors CLOCKS High freq. XTAL1 Med freq. XTAL2 Low freq. RC Oscillator (7.3728MHz) Watchdog Oscillator (400KHz) Figure 2-3: Block Diagram of Oscillator Control - P89LPC901 2003 Dec 8 FOSC2:0 CCLK Clock DIVM Oscillator Clock PCLK Timer 0 & 1 User’s Manual - Preliminary -...
  • Page 31: Block Diagram Of Oscillator Control - P89lpc902

    Philips Semiconductors CLOCKS RC Oscillator (7.3728MHz) Watchdog Oscillator (400KHz) Figure 2-4: Block Diagram of Oscillator Control - P89LPC902 2003 Dec 8 FOSC2:0 CCLK Clock DIVM Oscillator Clock PCLK Timer 0 & 1 User’s Manual - Preliminary - P89LPC901/902/903 RTCS1:0...
  • Page 32: Cpu Clock (cclk) Wakeup Delay

    Philips Semiconductors CLOCKS R C O scillato r (7.3728M H z) W atchd o g O scillator (400K H z) B au d rate G en erato r Figure 2-5: Block Diagram of Oscillator Control- P89LPC903 CPU Clock (CCLK) Wakeup Delay The P89LPC901/902/903 has an internal wakeup timer that delays the clock until it stabilizes depending to the clock source used.
  • Page 33: Low Power Select (p89lpc901)

    Philips Semiconductors User’s Manual - Preliminary - CLOCKS P89LPC901/902/903 Low Power Select (P89LPC901) The P89LPC901 is designed to run at 12MHz (CCLK) maximum. However, if CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a ’1’ to lower the power consumption further. On any reset, CLKLP is ’0’ allowing highest performance.
  • Page 34 Philips Semiconductors User’s Manual - Preliminary - CLOCKS P89LPC901/902/903 2003 Dec 8...
  • Page 35: Interrupts

    The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect, watchdog/ realtime clock, keyboard, and the comparator. The P89LPC902 supports 6 interrupt sources: timers 0 and 1, brownout detect, watchdog/ realtime clock, keyboard, and comparators 1 and 2. The P89LPC903 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog/ realtime clock, keyboard, and comparators 1 and 2.
  • Page 36: Summary Of Interrupts - P89lpc901

    Timer 1 Interrupt Brownout Detect Watchdog Timer/Real- WDOVF/ time Clock RTCF KBI Interrupt KBIF Comparator interrupt Table 3-3: Summary of Interrupts - P89LPC902 Interrupt Description Flag Bit(s) Timer 0 Interrupt Timer 1 Interrupt Brownout Detect Watchdog Timer/Real- WDOVF/ time Clock...
  • Page 37: External Interrupt Inputs

    Philips Semiconductors INTERRUPTS External Interrupt Inputs The P89LPC901/902/903 have a Keypad Interrupt function (see Keypad Interrupt (KBI) on page 79). This can be used as an external interrupt input. If enabled when the P89LPC901/902/903 is put into Power down or Idle mode, the keypad interrupt will cause the processor to wake up and resume operation.
  • Page 38: Interrupt Sources, Enables, And Power Down Wake-up Sources - P89lpc902

    Philips Semiconductors INTERRUPTS BOPD RTCF KBIF ERTC EKBI (RTCCON.1) WDOVF EWDRT EA (IE0.7) Figure 3-2: Interrupt sources, enables, and Power down Wake-up sources - P89LPC902 BOPD RTCF KBIF ERTC EKBI (RTCCON.1) WDOVF EWDRT EA (IE0.7) TI & RI/RI ES/ESR Figure 3-3: Interrupt sources, enables, and Power down Wake-up sources - P89LPC903 2003 Dec 8 User’s Manual - Preliminary -...
  • Page 39: I/o Ports

    Philips Semiconductors I/O PORTS 4. I/O PORTS The P89LPC901/902/903 has between 3 and 6 I/O pins. The exact number of I/O pins available depends on the clock and reset options chosen: Table 4-1: Number of I/O Pins Available Clock Source...
  • Page 40: Open Drain Output Configuration

    Philips Semiconductors I/O PORTS The third pullup is referred to as the "strong" pullup. This pullup is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pullup turns on for two CPU clocks quickly pulling the port pin high .
  • Page 41: Input-only Configuration

    Philips Semiconductors I/O PORTS Input-Only Configuration The input port configuration is shown in Figure 4-3. It is a Schmitt-triggered input that also has a glitch suppression circuit. (Please refer to the P89LPC901/902/903 datasheet, AC Characteristics for glitch filter specifications) input data...
  • Page 42: Additional Port Features

    Configuration SFR Bits Port PxM1.y P0.4 P0M1.4 P0.5 P0M1.5 P1.2 P1M1.2 P1.5 not configurable P3.0 P3M1.0 P3.1 P3M1.1 Table 4-4: Port Output Configuration - P89LPC902 Configuration SFR Bits Port PxM1.y P0.0 P0M1.0 P0.2 P0M1.2 P0.4 P0M1.4 P0.5 P0M1.5 P0.6 P0M1.6 P1.5...
  • Page 43 Philips Semiconductors User’s Manual - Preliminary - I/O PORTS P89LPC901/902/903 All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
  • Page 44 Philips Semiconductors User’s Manual - Preliminary - I/O PORTS P89LPC901/902/903 2003 Dec 8...
  • Page 45: Timers 0 And 1

    The “Timer” or “Counter” function is selected by control bit T0C/T in the Special Function Register TMOD. Timer 0 and Timer 1 of the P89LPC902 and P89LPC903, and Timer 1 of the P89LPC901 have four operating modes (modes 0, 1, 2, and 3), which are selected by bit-pairs (TnM1, TnM0) in TMOD.
  • Page 46: Mode 0

    Philips Semiconductors TIMERS 0 AND 1 TAMOD - P89LPC901 Address: 8Fh Not bit addressable Reset Source(s): Any reset Reset Value: xxx0xxx0B SYMBOL FUNCTION TAMOD.7-1 Reserved for future use. Should not be set to 1 by user programs. TAMOD.0 T0M2 Mode Select bit 2 for Timer 0. Used with T0M1 and T0M0 in the TMOD register to determine Timer 0 mode (P89LPC901).
  • Page 47: Mode 3

    Philips Semiconductors TIMERS 0 AND 1 Mode 3 When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 on Timer 0 is shown in Figure 5-7.
  • Page 48: Timer/counter 0 Or 1 In Mode 0 (13-bit Counter)

    Philips Semiconductors TIMERS 0 AND 1 PCLK T0 Pin* * T0 Pin functions available on P89LPC901 Figure 5-4: Timer/Counter 0 or 1 in Mode 0 (13-bit counter) PCLK T0 Pin* * T0 Pin functions available on P89LPC901 Figure 5-5: Timer/Counter 0 or 1 in Mode 1 (16-bit counter)
  • Page 49: Timer Overflow Toggle Output - P89lpc901

    Philips Semiconductors TIMERS 0 AND 1 PCLK T0 Pin* PCLK Figure 5-7: Timer/Counter 0 Mode 3 (two 8-bit counters) PCLK Figure 5-8: Timer/Counter 0 in Mode 6 (PWM auto-reload), P89LPC901. Timer Overflow toggle output - P89LPC901 Timer 0 can be configured to automatically toggle the T0 pin whenever the timer overflow occurs. This function is enabled by control bit ENT0 in the AUXR1 register.
  • Page 50 Philips Semiconductors User’s Manual - Preliminary - TIMERS 0 AND 1 P89LPC901/902/903 2003 Dec 8...
  • Page 51: Real-time Clock/system Timer

    Real-time Clock Source On the P89LPC901 the clock source for this counter can be either CCLK or the XTAL1-2 oscillator (XCLK) . On the P89LPC902 and P89LPC903 devicesthe clock source for this counter is CCLK. Please refer to Figure 2-3 "Block Diagram of Oscillator Control - P89LPC901"...
  • Page 52: Real-time Clock/system Timer Clock Source - P89lpc901

    Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER Table 6-1: Real-time Clock/System Timer Clock Source - P89LPC901 FOSC2 FOSC1 FOSC0 (UCFG1.2) (UCFG1.1) (UCFG1.0) 2003 Dec 8 RTCS1:0 CCLK Frequency High frequency crystal/DIVM Medium frequency crystal/DIVM Low frequency crystal/DIVM RC Oscillator/DIVM WDT Oscillator/DIVM external clock/DIVM User’s Manual - Preliminary -...
  • Page 53: Changing Rtcs1-0

    Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER Table 6-2: :Real-time Clock/System Timer Clock Source - P89LPC902/903 FOSC2 FOSC1 FOSC0 (UCFG1.2) (UCFG1.1) (UCFG1.0) Changing RTCS1-0 RTCS1-0 cannot be changed if the RTC is currently enabled (RTCCON.0 =1). Setting RTCEN and updating RTCS1-0 may be done in a single write to RTCCON.
  • Page 54: Rtccon Register

    Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER RTCCON Address: D1h Not bit addressable Reset Source(s): Power-up only Reset Value: 011xxx00B SYMBOL FUNCTION RTCCON.7 RTCF Real-time Clock Flag. This bit is set to ’1’ when the 23-bit Real-time clock reaches a count of ’0’. It can be cleared in software.
  • Page 55: Power Monitoring Functions

    Philips Semiconductors User’s Manual - Preliminary - POWER MONITORING FUNCTIONS P89LPC901/902/903 7. POWER MONITORING FUNCTIONS The P89LPC901/902/903 incorporates power monitoring functions designed to prevent incorrect operation during initial power- on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect.
  • Page 56: Power-on Detection

    Philips Semiconductors POWER MONITORING FUNCTIONS PMOD1-0 BOPD (UCFG1.5) (PCON.1-0) (PCON.5) 0 (erased) 11 (total power down) (brownout detect powered down) ≠ 11(any 1 (programmed) mode other than total power down) (brownout detect active) Table 7-1: Brownout Options. Power-On Detection The Power-On Detect has a function similar to the Brownout Detect, but is designed to work as power initially comes up, before the power supply voltage reaches a level where the Brownout Detect can function.
  • Page 57: Power Reduction Modes

    Philips Semiconductors POWER MONITORING FUNCTIONS Power Reduction Modes The P89LPC901/902/903 supports three different power reduction modes as determined by SFR bits PCON.1-0 (see Table 7-2): PMOD1 PMOD0 (PCON.1) (PCON.0) Normal Mode (Default) - no power reduction. Idle Mode. The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated.
  • Page 58: Power Control Register (pcon)

    Philips Semiconductors POWER MONITORING FUNCTIONS PCON Address: 87h Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION PCON.7 SMOD1 Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud rate source.
  • Page 59: Power Control Register (pcona)

    Philips Semiconductors POWER MONITORING FUNCTIONS PCONA Address: B5H Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION PCONA.7 RTCPD Real-time Clock Power down: When ’1’, the internal clock to the Real-time Clock is disabled. PCONA.6 Not used. Reserved for future use.
  • Page 60 Philips Semiconductors User’s Manual - Preliminary - POWER MONITORING FUNCTIONS P89LPC901/902/903 2003 Dec 8...
  • Page 61: Uart (p89lpc903)

    Philips Semiconductors User’s Manual - Preliminary - UART (P89LPC903) P89LPC901/902/903 8. UART (P89LPC903) The P89LPC903 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC903 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator.
  • Page 62: Sfr Space

    Philips Semiconductors UART (P89LPC903) SFR Space The UART SFRs are at the following locations: Table 8-1: SFR Locations for UARTs Register Description PCON Power Control SCON Serial Port (UART) Control SBUF Serial Port (UART) Data Buffer SADDR Serial Port (UART) Address...
  • Page 63: Framing Error

    Philips Semiconductors UART (P89LPC903) BRGCON Address: BDh Not bit addressable Reset Source(s): Any reset Reset Value: xxxxxx00B SYMBOL FUNCTION BRGCON.7-2 Reserved for future use. Should not be set to 1 by user programs. BRGCON.1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 & 3 (see Table for details) BRGCON.0...
  • Page 64: Serial Port Control Register (scon)

    Philips Semiconductors UART (P89LPC903) SCON Address: 98h Bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION SCON.7 SM0/FE The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit is read and written as SM0, which with SM1, defines the serial port mode. If SMOD0 = 1, this bit is read and written as FE (Framing Error).
  • Page 65: More About Uart Mode 0

    Philips Semiconductors UART (P89LPC903) SSTAT Address: BAh Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B SYMBOL FUNCTION SSTAT.7 DBMOD Double buffering mode. When set = 1 enables double buffering. Must be ’0’ for UART mode 0. In order to be compatible with existing 80C51 devices, this bit is reset to ’0’ to disable double buffering.
  • Page 66: More About Uart Mode 1

    Philips Semiconductors UART (P89LPC903) S1...S16 S1...S16 S1...S16 S1...S16 Write to SBUF Shift RxD (Data Out) TxD (Shift Clock) Write to SCON (Clear RI) Shift (Data In) TxD (Shift Clock) Figure 8-5: Serial Port Mode 0 (Double Buffering Must Be Disabled) More About UART Mode 1 Reception is initiated by detecting a 1-to-0 transition on RxD.
  • Page 67: More About Uart Modes 2 And 3

    Philips Semiconductors UART (P89LPC903) More About UART Modes 2 and 3 Reception is the same as in Mode 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.
  • Page 68: Double Buffering

    Philips Semiconductors UART (P89LPC903) Double Buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, provided the next character is written between the start bit and the stop bit of the previous character.
  • Page 69: The 9th Bit (bit 8) In Double Buffering (modes 1, 2 And 3)

    Philips Semiconductors UART (P89LPC903) Write to SBUF Tx Interrupt Single Buffering (DBMOD/SSTAT.7 = 0), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown Write to SBUF Tx Interrupt Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown, No End-...
  • Page 70: Multiprocessor Communications

    Philips Semiconductors UART (P89LPC903) - If DBISEL is ’1’ and INTLO is ’1’, a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter (which is also the last data). 7. If there is more data, the CPU writes to TB8 again.
  • Page 71 Philips Semiconductors UART (P89LPC903) since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.
  • Page 72 Philips Semiconductors User’s Manual - Preliminary - UART (P89LPC903) P89LPC901/902/903 2003 Dec 8...
  • Page 73: Reset

    Philips Semiconductors RESET 9. RESET The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
  • Page 74: Reset Sources Register

    Philips Semiconductors RESET RSTSRC Address: DFH Not bit addressable Reset Sources: Power-on only Reset Value: xx110000B (This is the power-on reset value. Other reset sources will set corresponding bits.) SYMBOL FUNCTION RSTSRC.7-6 Reserved for future use. Should not be set to 1 by user programs.
  • Page 75: Analog Comparators

    (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The output may be read in a register. On the P89LPC902 the output may also be routed to a pin. The comparator(s) may be configured to cause an interrupt when the output value changes.
  • Page 76: Comparator Input And Output Connections - P89lpc901

    (P0.5) CMPREF Vref Figure 10-2: Comparator Input and Output Connections - P89LPC901 (P0.4) CIN1A (P0.5) CMPREF Vref (P0.2) CIN2A Figure 10-3: Comparator Input and Output Connections - P89LPC902 2003 Dec 8 Comparator Change Detect Comparator 1 Change Detect Change Detect Comparator 2 User’s Manual - Preliminary -...
  • Page 77: Internal Reference Voltage

    Philips Semiconductors ANALOG COMPARATORS (P0.4) CIN1A (P0.5) CMPREF Vref (P0.2) CIN2A Figure 10-4: Comparator Input and Output Connections - P89LPC903 CN, OE = 0 0 CINnA CMPREF CN, OE = 1 0 CINnA Vref (1.23V) Internal Reference Voltage An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used. Please refer to the Datasheet for specifications.
  • Page 78: Comparator And Power Reduction Modes

    Philips Semiconductors ANALOG COMPARATORS an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator. Comparator and Power Reduction Modes The comparator(s) may remain enabled when Power down or Idle mode is activated, but the comparator(s) are disabled automatically in Total Power down mode.
  • Page 79: Keypad Interrupt (kbi)

    KBPATN.6-4,2,0 Pattern bit 6 - bit 4, bit 2, bit 0 2003 Dec 8 KBPATN.5 KBPATN.4 Figure 11-1: Keypad Pattern Register- P89LPC901 KBPATN.6 KBPATN.5 KBPATN.4 Figure 11-2: Keypad Pattern Register - P89LPC902 User’s Manual - Preliminary - P89LPC901/902/903 KBPATN.2 KBPATN.0...
  • Page 80: Keypad Pattern Register - P89lpc903

    Philips Semiconductors KEYPAD INTERRUPT (KBI) KBPATN Address: 93h Not bit addressable Reset Source(s): Any reset Reset Value: 11111111B SYMBOL FUNCTION KBPATN.5,4,2 Pattern bit 6, bit 4, bit 2 KBCON Address: 94h Not bit addressable Reset Source(s): Any reset Reset Value: xxxxxx00B...
  • Page 81: Keypad Interrupt Mask Register (kbm)) - P89lpc902

    Note: the Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective. Bit positions KBMASK.7, KBMASK.3, and KBMASK.1 should always be written as a ’0’. Figure 11-6: Keypad Interrupt Mask Register (KBM)) - P89LPC902 KBMASK...
  • Page 82 Philips Semiconductors User’s Manual - Preliminary - KEYPAD INTERRUPT (KBI) P89LPC901/902/903 2003 Dec 8...
  • Page 83: 12. Watchdog Timer

    Philips Semiconductors WATCHDOG TIMER 12. WATCHDOG TIMER The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. The watchdog timer can only be reset by a power-on reset.
  • Page 84: Feed Sequence

    Philips Semiconductors WATCHDOG TIMER Watchdog Oscillator ÷32 PCLK WDCLK after a watchdog feed sequence PRE2 DECODE PRE1 PRE0 Feed Sequence The watchdog timer control register and the 8-bit down counter (Figure 12-3) are not directly loaded by the user. The user writes to the WDCON and the WDL SFRs.
  • Page 85: Watchdog Timer Control Register

    Philips Semiconductors WATCHDOG TIMER WFEED1,#0A5h WFEED2,#05Ah SETB In timer mode (WDTE = 0), WDCON is loaded to the control register every CCLK cycle (no feed sequence is required to load the control register), but a feed sequence is required to load from the WDL SFR to the 8-bit down counter before a time-out occurs.
  • Page 86: P89lpc901/902/903 Watchdog Timeout Values

    Philips Semiconductors WATCHDOG TIMER Table 12-2: P89LPC901/902/903 Watchdog Timeout Values PRE2-PRE0 WDL in decimal) MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog Oscillator PRESCALER ÷32 PCLK PRE2 Figure 12-3: Watchdog Timer in Watchdog Mode (WDTE = 1) 2003 Dec 8 Timeout Period...
  • Page 87: Watchdog Timer In Timer Mode

    Philips Semiconductors WATCHDOG TIMER Watchdog Timer in Timer Mode Figure 12-4 shows the Watchdog Timer in Timer Mode. In this mode, any changes to WDCON are written to the shadow register after one watchdog clock cycle. A watchdog underflow will set the WDTOF bit. If IEN0.6 is set, the watchdog underflow is enabled to cause an interrupt.
  • Page 88 Philips Semiconductors User’s Manual - Preliminary - WATCHDOG TIMER P89LPC901/902/903 Note: When switching clocks, it is important that the old clock source is left enabled for 2 clock cycles after the feed completes. Otherwise, the watchdog may become disabled when the old clock source is disabled. For example, suppose PCLK (WCLK=0) is the current clock source.
  • Page 89: Periodic Wakeup From Power Down Without An External Oscillator

    Philips Semiconductors User’s Manual - Preliminary - WATCHDOG TIMER P89LPC901/902/903 Periodic wakeup from Power down without an external oscillator Without using an external oscillator source, the power consumption required in order to have a periodic wakeup is determined by the power consumption of the internal oscillator source used to produce the wakeup.The Real-time clock running from the internal RC oscillator can be used.
  • Page 90 Philips Semiconductors User’s Manual - Preliminary - WATCHDOG TIMER P89LPC901/902/903 2003 Dec 8...
  • Page 91: Additional Features

    AUXR1.6 EBRR UART Break Detect Reset Enable. If ’1’, UART Break Detect will cause a chip reset (P89LPC903). When writing to this register on the P89LPC901 or P89LPC902 devices, this bit position should be written with a zero. AUXR1.5 Reserved AUXR1.4...
  • Page 92 Philips Semiconductors ADDITIONAL FEATURES • MOV DPTR, #data16 Load the Data Pointer with a 16-bit constant. • MOVCA, @A+DPTR Move code byte relative to DPTR to the accumulator. • MOVXA, @DPTR Move data byte the accumulator to data memory relative to DPTR.
  • Page 93: 14. Flash Program Memory

    Philips Semiconductors FLASH PROGRAM MEMORY 14. FLASH PROGRAM MEMORY General description The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read and written as bytes. On-chip erase and write timing generation contribute to a user-friendly programming interface. The cell is designed to optimize the erase and programming mechanisms.
  • Page 94 Philips Semiconductors FLASH PROGRAM MEMORY ing to FMDATA. However, each location in the page register can only be written once following each LOAD command. Attempts to write to a page register location more than once should be avoided. FMADRH and FMADRL[7:4] are used to select a page of code memory for the erase-program function. When the erase-pro-...
  • Page 95: Flash Memory Control Register

    Philips Semiconductors FLASH PROGRAM MEMORY FMCON Address: E4h Not bit addressable Reset Source(s): Any reset Reset Value: SYMBOL FMCON.7-4 FMCON.3 FMCON.2 FMCON.1 FMCON.0 ;* Inputs: R3 = number of bytes to program (byte) R4 = page address MSB(byte) R5 = page address LSB(byte) R7 = pointer to data buffer in RAM(byte) ;* Outputs:...
  • Page 96: Accessing Additional Flash Elements

    Philips Semiconductors FLASH PROGRAM MEMORY unsigned char idata dbytes[16]; unsigned char Fm_stat; bit PGM_USER (unsigned char, unsigned char); bit prog_fail; void main () prog_fail=PGM_USER(0x1F,0xC0); bit PGM_USER (unsigned char page_hi, unsigned char page_lo) #define LOAD #define EP unsigned char FMCON = LOAD;...
  • Page 97: Erase-programming Additional Flash Elements

    Philips Semiconductors FLASH PROGRAM MEMORY Table 14-1: Flash elements accesable through IAP-Lite Element Address Description UCFG1 User Configuration byte 1. Boot Vector Boot vector Status Bit Status bit byte Security Security byte, sector 0 byte 0 Security Security byte, sector 1...
  • Page 98: Assembly Language Routine To Erase/program A Flash Element

    Philips Semiconductors FLASH PROGRAM MEMORY ;* Inputs: R5 = data to write(byte) R7 = element address(byte) ;* Outputs: None CONF WR_ELEM: FMADRL,R7 FMCON,#CONF FMDAT,R5 R7,FMCON A,R7 A,#0FH BAD: SETB Figure 14-4: Assembly language routine to erase/program a flash element unsigned char Fm_stat;...
  • Page 99: User Configuration Bytes

    Philips Semiconductors FLASH PROGRAM MEMORY #include <REG921.H> unsigned char READ_EL (unsigned char); unsigned char GET_EL; void main () GET_EL = READ_EL(0x02); unsigned char READ_EL (unsigned char el_addr) #define CONF unsigned char el_data; FMADRL = el_addr; FMCON = CONF; el_data = FMDATA;...
  • Page 100: Flash User Configuration Byte 1 (ucfg1)

    Philips Semiconductors FLASH PROGRAM MEMORY UCFG1 Address: xxxxh Default: 63h SYMBOL FUNCTION UCFG1.7 WDTE Watchdog timer reset enable. When set =1, enables the watchdog timer reset. When cleared = 0 , disables the watchdog timer reset. The timer may still be used to generate an interrupt.
  • Page 101: User Security Bytes

    Philips Semiconductors FLASH PROGRAM MEMORY USER SECURITY BYTES There are four User Sector Security Bytes (SEC0, ..., SEC3), each corresponding to one sector and having the following bit assignments: SECx Address: xxxxh Unprogrammed value: 00h SYMBOL FUNCTION SECx.7-3 Reserved (should remain unprogrammed at zero).
  • Page 102: Boot Vector

    Philips Semiconductors FLASH PROGRAM MEMORY Boot Vector BOOTVEC Address: xxxxh Factory default value: 00h SYMBOL FUNCTION BOOTVEC.7-5 Reserved (should remain unprogrammed at zero). BOOTVEC.4-0 Boot Vector. If the Boot Vector is selected as the reset address, the P89LPC901/902/903 will start execution at an address comprised of 00H in the lower eight bits and this BOOTVEC as the upper bits after a reset.
  • Page 103: Instruction Set

    Philips Semiconductors INSTRUCTION SET 15. INSTRUCTION SET Table 15-1: Instruction set summary Mnemonic ADD A,Rn ADD A,dir ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,dir ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,dir SUBB A,@Ri SUBB A,#data INC A INC Rn...
  • Page 104 Philips Semiconductors INSTRUCTION SET Mnemonic ANL dir,A ANL dir,#data ORL A,Rn ORL A,dir ORL A,@Ri ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,dir XRL A, @Ri XRL A,#data XRL dir,A XRL dir,#data CLR A CPL A SWAP A...
  • Page 105 Philips Semiconductors INSTRUCTION SET Mnemonic MOV dir,#data MOV @Ri,A MOV @Ri,dir MOV @Ri,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,dir XCH A,@Ri XCHD A,@Ri Mnemonic...
  • Page 106 Philips Semiconductors INSTRUCTION SET Mnemonic ACALL addr 11 LCALL addr 16 RETI AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel JMP @A+DPTR JZ rel JNZ rel CJNE A,dir,rel CJNE A,#d,rel...
  • Page 107: Revision History

    16. REVISION HISTORY 2003 Dec 8 Removed ENCLK bit from P89LPC902 and P89LPC903 TRIM SFRs. Modified Fig 2-1 to reflect ENCLK only on the P89LPC901. Removed RCCLK from TRIM SFR description (Fig2-1). Changed comparator SFR and bit names to match 89LPC9xx product line terminology.
  • Page 108 User’s Manual - Preliminary - Philips Semiconductors REVISION HISTORY P89LPC901/902/903 2003 Dec 8...
  • Page 109: Index

    Philips Semiconductors INDEX 17. INDEX Analog comparators 41, 75 configuration 75 configuration example 78 enabling 75 internal reference voltage 83 interrupt 77 power reduction modes 78 Analog comparators and power reduction 41 Block diagram 9 BRGCON writing to 24 Brownout detection 55...
  • Page 110 Philips Semiconductors INDEX block fill 7, 27, 35, 39, 45, 51, 55, 61, 73, 75, 79, 83, 91, 93, 103, 107 hardware reset 7, 27, 35, 39, 45, 51, 55, 61, 73, 75, 79, 83, 91, 93, 103, 107 Dual Data Pointers 91...
  • Page 111 Philips Semiconductors INDEX FLASH code 93 organization 25 Oscillator high speed crystal option 27, 28 low speed crystal option 27 medium speed crystal option 27 R-C option 28 watchdog (WDT) option 29 Pin configuration 7, 8 Port 0 12, 14, 15...
  • Page 112 Philips Semiconductors INDEX AUXR1 91 BRGCON 63 CMPn 75 KBCON 80 KBMASK 80, 81 KBPATN 79, 80 PCON 58 PCONA 59 RSTSRC 74 RTCCON 54 SCON 64 SSTAT 65 TAMOD 46 TCON 47 TMOD 45 TRIM 28, 29, 95 UCFG1 100...
  • Page 113 Philips Semiconductors INDEX double buffering in 9-bit mode 69 double buffering in different modes 68 framing error 63, 67 mode 0 65 mode 0 (shift register) 61 mode 1 66 mode 1 (8-bit variable baud rate) 61 mode 2 67...
  • Page 114 Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

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P89lpc903P89lpc901

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