Super I/O; Advanced Power Management; Intel ® Intelligent Power Node Manager (Nm) (Available When The Supermicro Power Manager "Spm" Is Installed In The System); Management Engine (Me) - Supermicro X9DRW-CF31 User Manual

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X9DRW-CF31/X9DRW-CTF31 Motherboard User's Manual
1-7

Super I/O

The Super I/O provides functions that comply with ACPI (Advanced Configuration
and Power Interface), which includes support of legacy and ACPI power manage-
ment through an SMI or SCI function pin. It also features auto power management
to reduce power consumption.
1-8

Advanced Power Management

The new advanced power management features supported by the motherboard
includes the following:
Intel
Intelligent Power Node Manager (NM) (Available
®
when the Supermicro Power Manager "SPM" is installed
in the system)
The Intel
Intelligent Power Node Manager (IPNM) provides your system with
®
real-time thermal control and power management for maximum energy efficiency.
Although IPNM Specification Version 1.5/20 is supported by the BMC (Baseboard
Management Controller), your system must also have IPNM-compatible Manage-
ment Engine (ME) firmware installed to use this feature.
Note: Support for IPNM Specification Version 1.5 or Version 2.0 depends
on the power supply used in the system.

Management Engine (ME)

The Management Engine, which is an ARC controller embedded in the PCH, pro-
vides Server Platform Services (SPS) to your system. The services provided by
SPS are different from those provided by the ME on client platforms.
1-9

Introduction to the IPMI Controller

This motherboard incorporates the Nuvoton WPCM450 IPMI Controller, which
integrates a RISC (Reduced-Instruction-Set-Computing) CPU Core with peripheral
capabilities required for a Baseboard Management Controller (BMC). The Nuvoton
WPCM450 IPMI Controller offers the user a superb solution to manage PC server
systems with great efficiency.
The BMC controller supports a 32Kb-instruction cache and a 32Kb-operand cache,
which can be switched between write-back and write-through. The instruction cache
offers a 4-way full-associative instruction TBL (Translation Lookaside Buffer) and a
64-way full-associative shared TBL. The memory management unit, which is embed-
ded on the chip, provides access to 4 Gb virtual address space. In addition, this
1-14

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