Processor 2/7-Clk, Misc - Clevo W540EU Service Manual

Schematic Diagrams
Processor 2/7- CLK, MISC
PU/PD for JTAG signals
1.05VS
3.3VS
If PROCHOT# is not used,
Sheet 3 of 42 then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS .
Processor 2/7-CLK,
MISC
Buffered reset to CPU
16,22
B - 4 Processor 2/7- CLK, MISC
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
R41 *51_04 XDP_TMS
R37 *51_04 XDP_TDI_R
XDP_PREQ#
R38 *51_04
R40 *51_04 XDP_TDO_R
R43 *51_04 XDP_TCLK
R39 51_04 XDP_TRST#
H_SNB_IVB#
17,29 H_SNB_IVB#
R293 *1K_04 XDP_DBR_R
H_CATERR#
3/23
R27 *10mil_short
17,28,29 H_PECI
H_PROCHOT# R26 56_1%_04 H_PROCHOT#_D
33 H_PROCHOT#
R36 *10mil_short
17 H_THRMTRIP#
14,29 H_PM_SY NC
R34 *10mil_short H_CPUPWRGD_R
17,29 H_CPUPWRGD
PMSY S_PWRGD_BUF R292 130_1%_04 VDDPW RGOOD_R
1.05VS
BUF_CPU_RST#
3.3VS
R296
75_04
BUF_CPU_RST#
R297 R295 43.2_1%_04
10K_04 D
Q14A
2
G MTDN7002ZHS6R
S
D
5
G Q14B
PLT_RST#
S MTDN7002ZHS6R
R294
C335
100K_04
*68p_50V_NPO_04
U13B
A28
BCLK
C26 A27
PROC_SELECT# BCLK#
AN34
SKTOCC#
A16
DPLL_REF_CLK
A15
DPLL_REF_CLK#
AL33
CATERR#
AN33 R8
CPUDRAMRST#
PECI SM_DRAMRST#
AL32 AK1
SM_RCOMP_0
PROCHOT# SM_RCOMP[0]
A5
SM_RCOMP_1
SM_RCOMP[1]
A4 SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29
XDP_PRDY#
PRDY #
AP27
XDP_PREQ#
PREQ#
AR26 XDP_TCLK
TCK
AR27 XDP_TMS
AM34 TMS AP30
XDP_TRST#
PM_SYNC TRST#
AR28 XDP_TDI_R
TDI
AP26 XDP_TDO_R
TDO
AP33
UNCOREPW RGOOD
AL35 XDP_DBR_R
DBR#
V8
SM_DRAMPWROK
AT28
XDP_BPM0_R
BPM#[0]
AR29 XDP_BPM1_R
BPM#[1]
AR30 XDP_BPM2_R
BPM#[2]
AR33 AT30 XDP_BPM3_R
RESET# BPM#[3] AP32
XDP_BPM4_R
BPM#[4]
AR31 XDP_BPM5_R
BPM#[5]
AT31 XDP_BPM6_R
BPM#[6]
AR32 XDP_BPM7_R
BPM#[7]
T2
H_PROCHOT#
Q3
G
C162
28 H_PROCHOT#_EC
MTN7002ZHS3
R105 47p_50V_NPO_04
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
Processor Pullups/Pull downs
H_PROCHOT# R22
CAD Note: Use pad sharing method
H_CPUPWRGD_R
10K_04
for following clock resistor placement
TRACE WIDTH 10MIL, LENGTH <500MILS
CLK_EXP_P 13
CLK_EXP_N 13
CLK_DP_P 13
DDR3 Compensation Signals
CLK_DP_N 13
CAD NOTE: All DDR_COMP signals
SM_RCOMP_0
R60
should be routed such that :-
- max length = 500 mils SM_RCOMP_1
R53
- trace width = 15mils and
SM_RCOMP_2 R57
- MB trace impedance < 68 mohms
(worst case resistance)
S3 circuit:- DRAM PWR GOOD logic
1.5VS_CPU
R62
200_1%_04
PMSY S_PWRGD_BUF
R61 *10mil_04
14,29 PM_DRAM_PWRGD
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R74
R75 *0_04
1K_04
Q1
MTN7002ZHS3
S D
CPUDRAMRST# R72 1K_04
DDR3_DRAMRST# 9,10
DRAMRST_CNTRL 6,13
R76 C151
4.99K_1%_04 0.047u_10V_X7R_04
1.05VS
62_04
R33
140_1%_04
25.5_1%_04
200_1%_04