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Schematic Diagrams
Processor 2/7
PU/PD for JTAG signals
1.05VS_VTT
3.3VS
If PROCHOT# is not used,
then it must be terminated
Sheet 3 of 50
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
Processor 2/7-CLK,
MISC
Buffered reset to CPU
12,22,28
PLT_RST#
B - 4 Processor 2/7- CLK, MISC
- CLK, MISC
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
R498
51_04
XDP_TMS
XDP_TDI_R
R494
51_04
XDP_PREQ#
R496
*51_04
R503
51_04
XDP_TDO_R
R499
51_04
XDP_TCLK
R495
51_04
XDP_TRST#
H_SNB_IVB#
23
H_SNB_IVB#
R491
*0_04
R107
1K_04
XDP_DBR_R
H_CATERR#
R106
*0_04
R516
0_04
23,34
H_PECI
H_PROCHOT#
R116
56_1%_04
H_PROCHOT#_D
40,42
H_PROCHOT#
R493
*10mil_short
23
H_THRMTRIP#
20
H_PM_SY NC
H_CPUPWRGD_R
R517
*10mil_short
23
H_CPUPWRGD
PMSY S_PWRGD_BUF
R199
130_1%_04
VDDPWRGOOD_R
1.05VS_VTT
BUF_CPU_RST#
3.3VS
R213
75_04
BUF_CPU_RST#
R207
R212
43.2_1%_04
10K_04
D
Q17B
5
G
MTDN7002ZHS6R
S
D
2
G
Q17A
S
MTDN7002ZHS6R
34
H_PROCHOT#_EC
R206
R205
*1.5K_1%_04
C315
100K_04
R211
68p_50V_NPO_04
*750_1%_04
CAD Note: Use pad sharing method
U36B
for following clock resistor placement
A28
BCLK
CLK_EXP_P 19
C26
A27
PROC_SELECT#
BCLK#
CLK_EXP_N 19
AN34
SKTOCC#
A16
CLK_DP_P 19
DPLL_REF_CLK
A15
CLK_DP_N 19
DPLL_REF_CLK#
AL33
CATERR#
AN33
R8
CPUDRAMRST#
PECI
SM_DRAMRST#
AL32
AK1
SM_RCOMP_0
PROCHOT#
SM_RCOMP[0]
A5
SM_RCOMP_1
SM_RCOMP[1]
A4
SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29
XDP_PRDY #
PRDY#
AP27
XDP_PREQ#
PREQ#
AR26
XDP_TCLK
TCK
AR27
XDP_TMS
AM34
TMS
AP30
XDP_TRST#
PM_SY NC
TRST#
AR28
XDP_TDI_R
TDI
AP26
XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35
XDP_DBR_R
DBR#
V8
SM_DRAMPWROK
AT28
XDP_BPM0_R
BPM#[0]
AR29
XDP_BPM1_R
BPM#[1]
AR30
XDP_BPM2_R
BPM#[2]
AR33
AT30
XDP_BPM3_R
RESET#
BPM#[3]
AP32
XDP_BPM4_R
BPM#[4]
AR31
XDP_BPM5_R
BPM#[5]
AT31
XDP_BPM6_R
BPM#[6]
AR32
XDP_BPM7_R
BPM#[7]
Iv y Bridge_rPGA_2DPC_Rev 0p61
H_PROCHOT#
Q14
G
C173
MTN7002ZHS3
R148
47p_50V_NPO_04
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
Processor Pullups/Pull downs
1.05VS_VTT
H_PROCHOT#
R115
62_04
H_CPUPWRGD_R
10K_04
R125
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
CAD NOTE: All DDR_COMP signals
SM_RCOMP_0
R183
140_1%_04
should be routed such that :-
- max length = 500 mils
SM_RCOMP_1
R520
25.5_1%_04
- trace width = 15mils and
SM_RCOMP_2
R521
200_1%_04
- MB trace impedance < 68 mohms
(worst case resistance)
S3 circuit:- DRAM PWR GOOD logic
3.3V
3.3V
C300
1.5VS_CPU
R194
R193
*200_04
*100K_04
R200
200_1%_04
1
20
PM_DRAM_PWRGD
4
PMSY S_PWRGD_BUF
2
20,37
1.8VS_PWRGD
U11
*MC74VHC1G08DFT1G
R209
C301
*39_04
*0.1u_10V_X5R_04
R208
0_04
Q16
G
35,37,38
SUSB
*MTN7002ZHS3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R281
R282
*0_04
1K_04
Q20
MTN7002ZHS3
CPUDRAMRST#
S
D
R276
1K_04
DDR3_DRAMRST# 9,10
DRAMRST_CNTRL 6,19
R275
C707
4.99K_1%_04
0.047u_10V_X7R_04
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