Timing Circuits; Status Latch; Wait Logic - Fluke 8506A Instruction Manual

TO
/iP
TO
fjP
15.3R
MH7
=
02
U19
SYNC
STSTB
FROM
/jP
.
TO STATUS
LATCH
Figure
3-11.
Timing
Circuits
3-49.
ADDRESS AND
DATA BUSES
3-50.
ROM
locations are
decoded from
A
14
and
A
13,
as
chip
selects
and from
AO
through
A
12.
RAM
locations
are
decoded from
A
14
and
A1
1,
as
chip
selects,
and from
AO
through
A
10.
External
modules
are selected
by
setting
A15
high.
Inverted forms
of
A8
through
A
14 are sent out
as
ICO
through 1C6 on
the
unguarded
bus.
The
data bus
lines
(DO through D7)
are connected
directly to internal
memory
and through
tristate
buffers to the external data
bus
(IDO through
ID7).
3-51.
RESET
3-52. Refer
to
Figure
3-12.
Shaped
line
frequency
pulses
are applied
to
U2
and
U3, providing
a
hardware
reset
on
powerdown, power
up, or
for missing
line
cycle pulses. In
any
of these three
reset
conditions, retriggerable
one
shot
U2 (T—
40 ms)
generates
a reset pulse for
up
counter U3.
After the
reset
to
U
3
is
removed
(delayed
Vcc
high or a
line
frequency
pulse),
U3
must be clocked by
eight
line
frequency
pulses to raise
Q4
high and remove
the
reset
signal.
The
reset
pulse
is
held for eight
line cycles to
allow
time for the
power
supplies
and microprocessor
oscillator
to stabilize.
3-53.
STATUS LATCH
3-54.
Refer
to
Figure
3-13.
During
the
first
state of every
machine
cycle,
the microprocessor sends out a
status
8508A
Figure 3-13. Status Latch
word on
the data bus.
This
status
word
contains the
information
for
external logic to synchronize with
microprocessor
activity
(e.g.,
memory
read, interrupt
acknowledge).
Clock
signal
STSTB
(from U19)
clocks
this
information
into
quad
D-type
flip-flop
U12
for use
during the
machine
cycle.
External
interrupts
are also
latched into the status latch for synchronization
to the
microprocessor.
3-55.
WAIT LOGIC
3-56.
Refer
to
Figure
3-14.
When
the
microprocessor
addresses
an
external
module,
the wait
state logic
forces
the
microprocessor
to enter a wait
state
and allow
the
module
time
to
respond.
When
the
microprocessor
acknowledges an
interrupt, the wait
state
is
similarly
forced to allow time for the interrupt
vector to be
generated.
A
wait
state
is
entered
when
a
rising edge
on
STOP
(the
clock input
Ul)
sets
READY
low.
Clock
3-11