Fluke 8506A Instruction Manual page 315

8506A
LIST
OF
MNEMONICS
A0-A15 Address bus
on
controller
ACK
Acknowledge
signal
from module
ACKiNT
Interrupt
generated
when
module does
not
respond
CPUINT
Interrupt signal for /jP
CPUREADY
Ready
signal
for
fjP
CPURESET
Reset
signal
D0-D7 Data bus
on
controller
DBIN
Data bus input signal (from
fjP)
DLDACK
Delayed
version
of
ACK
EXTCOM
Module communication
signal
EXTINT
Interrupt
from
module
FLINE
Shaped
line
frequency
signal
SxFLINE
8
times
line
frequency
FRONT/REAR
Front or rear input signal
IC0-1C7
Module address/control bus
ICENABLE
Enable
module
address
signal
ID0-ID7
Module
data
bus
INA
Interrupt
acknowledge
signal
in
response
to
EXTINT
INP I/O status signal
INTA
Interrupt
acknowledge
status signal
INTCLR
Clear interrupt signal
LINEREF
Line reference
signal,
bus
input
on
RTS
MARKINT
Interrupt to
synchronize
to line
frequency
01
One
phase
of
/iP
clock
02
Other phase
of
fjP
clock
OUT
I/O status signal
READY
Signal
to
generate
CPUREADY
RESET
Reset signal
RUN
Exit
wait state signal
SCANADV
Scan advance
signal,
A/D
conversion
complete
STOP
Enter wait state signal
STSTB
Clock signal to latch
/jP status
SYNC
Signal
from
/jP,
used
to
generate
STSTB
SYNCDEXTINT
Synchronized
interrupt
from
module
Vbb -5V supply
Vcc
+5V
supply
Vdd
+12V
supply
Vgg -12V supply
Vss
Logic
common
WAIT
fjp
in
wait state signal
WR
Write data signal
from
/jP
8-3