Dc Signal - Fluke 8506A Instruction Manual

8506A
address-! CO,
1,
6,
high.
For
either direct address, the
condition of
ID7
(high for disable)
is
latched into
U23
to
enable an
indirect
address. Digit
segment
address-ICl,
5
high,
and
d igit-annunciator
select
address-ICO,
5
are
both
indirect addresses.
Data
is
clocked into the
registers
upon
termination of the address.
An
update sequence
is
as
follows:
1
.
Register
1
is
addressed with
all
data
lines
low
to
blank the
annunciator
display
and
enable
indirect
addressing.
2.
Register 2
is
addressed
indirectly
with data
lines
low
to
blank the
digit
display.
3.
Register
3
is
addressed indirectly with
all
data
lines
high
to
turn off
all
LEDs,
disable the switch
matrix,
and
disable indirect addressing.
4.
Register
1
is
addressed with
ID7
low
to
enable
indirect
addressing and with
either
annunciator
segment
data or
digit
7SD
data on
IDO-6.
The
data
is
latched
and
applied
to
the
annunciator
LEDs
(or
to digit
7SD).
5.
Register 2
is
addressed with
digit
segment data
on
IDO-7 (U23
is
not clocked
by
this
address
so
ID7
may
be high
without
disabling indirect addressing).
The
data
is
latched
and
applied to the
digit
LEDs.
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indirect
addressing)
and one of the data
lines,
IDO-6
low
to
enable
one
digit
LED
and one
annunciator
LED. One
bank
of the switch
matrix
is
also enabled.
7.
The
output buffer
is
addressed enabling
the
data
from
the
previously enabled switch
bank
to
be
placed
on
the
data
bus.
One
or
more
lines being
low
indicates
a
change
is
desired.
This address
also
keeps the
kill
circuit
charged.
3-67.
The
seven
steps just
outlined are required
for
one
digit-annunciator-switch
bank
update.
The
process
is
repeated seven times for a
complete
update.
The
kill
circuit
is
used
to
blank
the
display
if
the Controller
discontinues addressing the front panel.
3-68.
DC
Signal Conditioner
3-69. Relays
K1 and
K2
control the input to the
DC
Signal Conditioner
and
the attenuation of the input
(Figure
3-18). If
both
relays
are energized, the input
is
from
the Volt/
O
input sense terminals with
*
64
attenuation.
If
just
KI
is
energized, the input
is
from
the
Volt/a
input terminals with
no
attenuation.
If just
K2
is
energized, the input
is
from
RT1
with
no
attenuation.
Q10,
Q
1
1 ,
CR3, and
CR4
provide overvoltage
protection.
3-70.
A
differential
amplifier
(Q18,
Q
1
9)
drives U3.
FET
switched (Q14,
Q15, Q16)
control the gain of
QI8
and Q37.
An
output voltage
swing
of
±20V
is
achieved
through bootstrapping;
U4
provides
a
bootstrap
for
Q38
and Q37, and
U5 and
U6
provide a bootstrap
for
U3
and
U4.
Current
sink
and
source for
Q18 and
Q
19 are
provided by
Q38 and Q37
respectively.
3-71.
The
DC
Signal Conditioner
is
addressed by
ICO,
3,
4
high.
Data on IDO-3
is
latched
up and decoded
to
determine
which
switches
and
relays will
be
energized.
Figure 3-18 includes
an example of
the relay driver used
to
minimize thermal changes
in
the
relays
between
the
on
and
off states.
RC
coupling
between
the
decoder and
the
relay
driver provide voltage swings
up
to
4V
or
down
to
0V
to
ensure positive relay action.
Steady
state
voltages of
1.45V
(off)
and
2.75V
(on)
minimize current difference
between
the
on and
off states
while maintaining the
relay
state
under
all
conditions.
3-72. Fifter/Extemal
Reference
3-73.
All inputs
to
the
A/D
Converter are routed
through
the
Filter/
External Reference module. Refer
to
Figure 3-19.
External
measurements
are
made
by
multiplexing the three
filter
module
inputs
to
the
A/D
Converter.
Q18,
Q
1 9,
and
Q20
switch the
signal
conditioner
input, the external reference
LO
input,
and
the external reference
HI
input
respectively.
Data
controlling the switches
is
latched
into
U1 upon
termination of
the address (IC1,
3,
4
high).
3-74.
Three-pole,
active
Bessel
filters
(U3 and U4) have
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f i
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n
CF
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pH
if
f'jf
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muy
be
selected
from
the
front
input panel
for
application
to
the signal conditioner
input.
Bypass
is
automatically
selected for
external reference inputs
and
may
be
selected
for signal
conditioner
inputs.
The
combination of
Q32,
Q25, Q23, Q24,
or
Q21,
Q22
is
turned
on
to select a
filter
mode.
3-75.
A
dual, super-beta transistor
in a differential
configuration
(Q27)
drives
U5.
A
current source (Q26)
and
sink
(Q30) bias
Q27.
Enough
current
is
drawn
through
R19
by Q26
to
bootstrap the input amplifier,
Q27,
5V
above
the output.
Gain
of the amplifier
is
set at
one by
the
combination
of
R21 and
the input
resistors.
The
external reference inputs have additional
series
resistors
located
on
the
Front/
Rear
Input Assembly.
3-70. Fast
R
z A/D
Converter
3-77.
The
Fast
R
2
A
/
D
Converter
may
be separated
for
analysis into
two component
groups:
analog and
digital.
Analog
circuitry
is
responsible
for
producing
a
voltage reference, for
summations, and
for
remainder
amplification
and
storage. Digital circuitry interfaces the
analog circuitry to the Contoller
and
is
responsible for
reference selection,
decision
in
the
summation
process,
remainder channel control,
and
autozeroing. Since
functions within
the
A/D
Converter
are either directly
controlled
by
the Controller
module
via the
data bus or
are
clocked through
their
operations by
the
Controller
3-15