Fluke 8506A Instruction Manual page 231

3505A/8506A-05
605-7.
OPERATING FEATURES
605-8.
Attached
to the
assembly and
accessible
through
a port on
the rear
panel.
(Figure 605-1) are a standard
specified connector,
five
address switches and
a
Talk Only
Mode
switch.
The
connector
is
standard
for the
IEEE
bus
and
is
specified
by
the
standard document. The
address of
the instrument
is
set
using the
five
address
switches.
The
characters used to address the instrument
in
the talk
and
listen
mode
are
given
in
Table
605-1.
The
five
low
order
bits
of the message determine
the address, the next two
higher
bits
differentiate between
the
Talk and
Listen
modes.
Normal
operation allows
the instrument
to
both
talk
and
listen to the bus.
The
Listen
mode
can be disabled
with the Talk
Only
switch,
if
desired.
605-9.
OPERATING NOTES
605-10.
Interface Control
605-11. Information
is
input to the
interface
from
the
controller
on
the system
bus,
which
contains
eight
data
lines,
three
handshake
lines
and
five
bus
management
lines.
Control of
the
handshake and management
lines
is
from
the controller
and
will
vary with the
controller used.
Refer to the instructions
with the system controller for the
information on
how
to obtain the correct
level,
on
these
lines.
The
lines
and
a
brief
explanation of
their
function
are given
in
Table
605-3.
Refer
to
the
IEEE
488-1975
Standard Manual
for a further explanation of
their
function,
605-12.
interface
Messages
605-13. Multiple
line
messages are input
to the interface
from
the controller using
the data
lines.
The
messages
used within
the instrument
are
listed
with
their
codes
in
Table
605-4. Further information
on
the
messages can be
obtained from
the
IEEE
488-1975 Standard Manual.
605-14.
Status Request Responses
605-15.
If
enabled by
the applicable Interface Interrupt
Enable Code,
a service request
(SRQ)
can be generated
within the
interface by
either
an
error or ready condition.
When
the instrument
is
addressed during a
serial poll
operation
by
the
IEEE
488
Controller,
and an
interrupt
is
generated,
the
response
byte will
be a zero for ready or
the
numeric
of
the applicable Error Code.
If
the
SRQ
was
not
generated, the response
is
a null
character (binary
000000000)
to the
controller.
§0$"16„
THEORY
OF OPERATION
605-17. The
IEEE
Interface provides
for
communication
between
the
IEEE
system bus
and
the
DMM
internal bus
structure.
The
IEEE
system bus
is
defined by
the
IEEE
standard; the
DMM
internal
bus
structure
is
discussed
in the
instrument
Instruction
Manual. System
bus
signal
lines will
be
referred to
by
their
mnemonic
designators
(refer to
Table 605-3
for
definitions).
605-18.
The
IEEE
Interface consists
of
two
interconnected pcb's
in
one module. Each
pcb
will
have
its
own
reference designator system.
To
distinguish
between
the two, reference designators
mounted on
the
Piggyback
board
will
be followed by a (PB).
605-19. Data
Lines
605-20.
System
bus data
lines
(DIO
1-08) are applied
to
the interface
through
receiver/ drivers,
U21 and
U24.
The
receivers consist of noninverting
buffers, while the drivers
are gates with a
common
enable
line
from
U32-8.
NOTE
True conditions on
the system data bus
are
defined as a low;
true conditions
on
the
instrument bus
are defined as
a high
.
Outputs from
the
data
line receiver drivers are applied
directly to address decoders,
U19 and
U12, through
address switch SI
to
address decoders
U6
and U3, and
through
inverters to
a data
register
consisting of
U30 and
part
of U31.
605-21.
The
internal
DMM
data bus
is
applied to a
response
register
consisting of
U26
and U29. This
register
latches
data up
for application to the system bus
lines
(the
system bus
requires that data be
held longer than
is
desirable
to
tie
up
the instrument
controller). Instrument
data
is
also applied to the control
register
on
the
Piggyback board (Ull-PB,
U16-PB, U14-PB).
605-22.
Addresses
605-23. Instrument address
lines
(IC0-IC6) are applied
to
address decoders located on
the
Piggyback
board. All
of the following
listed
addresses cause an
ACK
to
be
returned
to the
instrument
controller through
U6
(PB)-l.
1.
IC 1,5 and
4 High:
Decoded U12
(PB)-6
to
enable
the response
register.
2.
IC
6,
4
and
3
High:
U12(PB)-iO
to
clock data
into
the control
register;
if
IDO
is
high,
this
address
also causes a
Return
to
Local
signal
from
U8(PB)-3.
3.
IC
5,
3
and
0
High: Decoded by U13(PB)-6
to
cause a software
reset
through U8(PB)~!0.
4.
IC
6-,
0
and 4 High: Decoded
by U13(PB)-9
to
enable the status register
(U28 and
part of U31).
5.
IC,
6, 1
and
4
High: Decoded by U13(PB)-10
to
enable the data
register
(U30 and
part of U31).
605-24.
Addresses
to
the
IEEE
Interface
from
the
system are received
on
the
data
lines
when
ATN
is
true.
Address
switch SI routes
My
Listen
Address
(MLA)
and
My
Talk Address
(MTA).
Decoding
for
MLA
is
done by
U6-13;
the
DAV
signal clocks
this
address into Ull-1.
The
MTA
flip-flop
Ull-1
is
cleared
by
the
UNL
(Unlisten) signal
(decoded by
IJ
19-13).
The
Message
Decoder
(U9,
U5
and U8)
is
enabled by
the
ATN
and
U
12-10
(decoded by DI02, DI06,
DI07).
605-3