Fluke 8506A Instruction Manual page 102

8506
.
generator
U19
then synchronizes
READY
to
the timing
requirements
of the
microprocessor and
pulls
CPU
READY
low.
3-57.
To
exit
the wait
state,
RUN
(the clear input to
U
1
must be pulled low.
Two
events cause
this to
happen.
ACKINT
is
asserted
by
the interrupt circuitry
if
the
addressed
module does
not return an
ACK
in a specific
time period. Alternately,
DLDACK
is
asserted.
DLDACK
is
asserted
by a
module
returning
an
ACK
or
by response to
a
MARK
I
NT.
3-58.
ACK
LOGIC
3-59. Refer
to
Figure
3-15.
When
a
module
is
addressed
by
the controller or
is
enabled
for interrupt identification
by IN
A,
it
must
return
an
ACK
(high)
to
complete
the
handshake.
ACK
is
delayed
about
1.6
us to produce
DLDACK.
DLDACK
is
also
generated
in
a
MARK
INT
interrupt
response
cycle.
3-60.
INTERRUPTS
3-61.
Two
possible internal interrupts
(MARK
INT
and
ACKINT)
and
three possible external interrupts
(EXTINT)
are able to drive
CPUINT
high
and
interrupt
the microprocessor.
The
microprocessor samples
the
interrupt
line
at
the end of each
machine
cycle.
If
an
interrupt exists, the
microprocessor
asserts
INT
A
in
the
status
word
of the next
instruction fetch
machine
cycle.
External
logic
is
thereby enabled
to
place
an
interrupt
vector (and not the next instruction)
on
the data
bus.
Refer
to Figure 3-16.
Figure 3-15.
ACK
Logic
3-12