HP 16550A User Reference page 65

100-mhz state/500-mhz timing logic analyzer
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The Format Menu
Setup/Hold Field (State only)
The relationship of the clock signal and valid data under the default setup
and hold is shown in the figure below.
If
the relationship of the clock signal and valid data is such that the data is
valid for 1 ns before the clock occurs and 3 ns after the clock occurs, you
will
want to use the 1.0 setup and 2.5 hold setting.
Your choice
Setup
I
Hold
1. 0
I
2. 5
Clock Position in Valid Data
4-24
VALID
DATA
4ns
1ns
2.5ns
16550Ml1

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