HP 16550A User Reference page 244

100-mhz state/500-mhz timing logic analyzer
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Timing Analysis
Sample Period Accuracy
Channel-to-Channel Skew
Time Interval Accuracy
Triggering
Sequencer Speed
State Sequence Levels
Timing Sequence Levels
Max. Occurrence Counter Value
Pattern Recognizers
Maximum Pattern Width
Range Recognizers
Range Width
Timers
Timer Value Range
Glitch/Edge Recognizers
Maximum Glitch/Edge Width
Specifications and Characteristics
Characteristics
0.01 % of sample period
2 ns, typical
±(sample period+ chan-to-chan skew
+ 0.01% of time reading)
125 MHz, maximum
12
10
1,048,575
10
102 channels in a 1 card configuration.
204 channels in a 2 card configuration.
2
32
bits each
2
400 ns to 500 seconds
2
(timing only)
102 channels in a 1 card configuration.
204 channels in a 2 card configuration.
I
12-5

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