HP 16550A User Reference page 61

100-mhz state/500-mhz timing logic analyzer
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I
The Format Menu
Pod Threshold Field
USER
When USER is selected as the threshold level, the data signals must reach a
user selectable value between -6.0 volts to +6.0 volts.
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Format 1
State Acquisition Mode
Full Channel /4K Memory/lOOMHz
Clock Inputs
MACH 1
81
Lab2
Lab3
Lab4
Lab5
Lab6
Lab7
Lab8
Pod Threshold Field
4-20
;;
KJ
Pod threshold field
, - - - - - - ,
Pod Threshold
selection menu

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