Sandy Bridge Processor 7/7 - Clevo W150HRM Service Manual

Sandy Bridge Processor 7/7

C FG S tr ap s fo r Pr oc ess or
PE G Static Lane Reversal - CFG 2 is for the 16x
CF G2 1:(Default) Normal Oper ation; La ne #
definition matches sock et pin ma p de finition
0:Lane Reversed
C F G 2
R 5 0 3 * 1K _ 0 4
Di splay Port Presence Strap
1:(Default) Disabled; N o Physica l Di splay Port
CF G4
attached to Embedded Di splay Por t
0:Enabled; An external Display P ort device is
connected to the Embedd ed Displa y Po rt
C F G 4 R 4 9 3 * 1K _ 0 4
PCIE Port Bifurcation Straps
11: (Default) x16 - De vice 1 fu nctions 1 and 2 disabled
10: x8, x8 - Devic e 1 funct ion 1 enabled ; function 2 disab led
C FG [ 6: 5]
01: Reserved - (De vice 1 fu ncti on 1 disabled ; function 2 e nable d)
00: x8,x4,x4 - Dev ice 1 fun ctio ns 1 and 2 enabled
C F G5 R 49 2 *1 K _ 04
C F G6 R 50 0 *1 K _ 04
R 5 1 4
3. 3 V
H _ S N B _I V B #_ P W R C T R L
PEG DEFER TR AINI NG
1: (Defau lt) PEG T rain imme diately following x xRESETB d e asserti on
CF G 7
0: PEG Wa it for BI OS for tr aining
C F G 7 R 4 9 1 * 1K _ 0 4
Sandy Bridge Processor 7/7 ( RESERVED )
U 4 9E
C F G0 A K 2 8
A K 2 9 C F G[ 0 ]
C F G[ 1 ]
C F G2 A L2 6
A L2 7 C F G[ 2 ]
C F G[ 3 ]
C F G4 A K 2 6
C F G[ 4 ]
A L2 9
C F G5
C F G[ 5 ]
C F G6 A L3 0
A M3 1 C F G[ 6 ]
C F G7
C F G[ 7 ]
A M3 2
A M3 0 C F G[ 8 ]
C F G[ 9 ]
A M2 8
A M2 6 C F G[ 1 0 ]
C F G[ 1 1 ]
A N 2 8
A N 3 1 C F G[ 1 2 ]
C F G[ 1 3 ]
A N 2 6
A M2 7 C F G[ 1 4 ]
C F G[ 1 5 ]
A K 3 1
A N 2 9 C F G[ 1 6 ]
C F G[ 1 7 ]
H _ C P U _ R S V D 1 A J3 1
V A X G_ V A L _ S E N S E
A H 3 1
H _ C P U _ R S V D 2
V S S A X G _V A L_ S E N S E
H _ C P U _ R S V D 3 A J3 3
V C C _ V A L _S E N S E
H _ C P U _ R S V D 4 A H 3 3
V S S _ V A L _ S E N S E
A J2 6
R S V D 5
V R E F _C H _ A _ D I M M B 4
R S V D 6
V R E F _C H _ B _ D I M M D 1
R S V D 7
F 2 5
F 2 4 R S V D 8
R S V D 9
F 2 3
D 2 4 R S V D 1 0
R S V D 1 1
G2 5
G2 4 R S V D 1 2
R S V D 1 3
E 2 3
D 2 3 R S V D 1 4
R S V D 1 5
C 3 0
A 3 1 R S V D 1 6
R S V D 1 7
B 3 0
B 2 9 R S V D 1 8
R S V D 1 9
D 3 0
B 3 1 R S V D 2 0
R S V D 2 1
A 3 0
C 2 9 R S V D 2 2
R S V D 2 3
10 K _ 1 %_ 0 4 J2 0
R S V D 2 4
B 1 8
R S V D 2 5
R 5 1 6 *1 0 mi l _ sh o rt H _ S N B _ I V B # _ P W R C TR L _R A 1 9
V C C I O _S E L
J1 5
R S V D 2 7
On CRB
H_SNB_IVB#_PWRCTR L = low, 1.0V
H_SNB_IVB#_PWRCTR L = high/ NC, 1.05V
P Z 98 8 2 7-3 6 4 B -01 F
? DIMM? ? ?
1 . 5 V
R 6 4 2 *0 _ 0 4
R 1 5 5
Q9 1K _ 1 % _0 4
L 7
*A O 3 40 2 L
R S V D 2 8
A G7 V R E F _ C H _A _D I MM S D M V R E F _D Q_ D I M 0
R S V D 2 9
A E 7
R S V D 3 0 A K 2
R S V D 3 1
W 8
R 1 49 R 1 5 0
R S V D 3 2
*1 K _0 4
1K _ 1 % _0 4
A T 26
R S V D 3 3
A M3 3
R S V D 3 4 A J 27
R S V D 3 5
D R A M R S T _ C N TR L 3, 1 9
1. 5 V
T 8
R S V D 3 7
J 16 R 6 4 3 *0 _ 0 4
R S V D 3 8 H 1 6
R S V D 3 9
G1 6
R S V D 4 0
R 15 9
Q1 0
*A O 3 40 2 L 1 K _ 1% _ 0 4
V R E F _ C H _B _D I MM S D M V R E F _ D Q _ D I M1
A R 3 5
R S V D 4 1
A T 34
R S V D 4 2
A T 33
R 1 53 R 16 0
R S V D 4 3
A P 3 5 *1 K _0 4
R S V D 4 4
A R 3 4
1 K _ 1% _ 0 4
R S V D 4 5
B 3 4
D R A MR S T_ C N T R L 3 , 1 9
R S V D 4 6
A 3 3
R S V D 4 7
A 3 4
R S V D 4 8 B 3 5
R S V D 4 9
C 3 5
R S V D 5 0
A J 32
R S V D 5 1
A K 3 2
R S V D 5 2
A H 2 7
V C C _ D I E _ S E N S E
A N 3 5
R S V D 5 4 A M3 5
R S V D 5 5
A T 2
R S V D 5 6
A T 1
R S V D 5 7
A R 1
R S V D 5 8
B 1
K E Y
3, 6 , 9 , 1 0, 25 , 2 9 , 35 , 3 7 , 38 1 . 5 V
2, 3 , 1 1 , 12 , 1 6 , 1 8, 1 9 , 2 0, 2 2 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 33 , 3 5 , 37 , 3 8 , 39 3 . 3 V
Schematic Diagrams
& TRACE? ?
M V R E F _D Q_ D I M MA 9
C 3 57
0 . 1 u _1 0 V _ X 5R _0 4
Sheet 8 of 49
Sandy Bridge
M V R E F _D Q_ D I M MB 1 0
C 3 6 7 Processor 7/7
0 . 1 u_ 1 0V _X 5 R _ 0 4
Sandy Bridge Processor 7/7 B - 9