Sandy Bridge Processor 1/7 - Clevo W150HRM Service Manual

Sandy Bridge Processor 1/7

CPU
H 1 6 H 1 5 H 8
H 8 _ 0 D 4 _ 4 H 8 _0 D 4 _4 H 8 _ 0D 4 _ 4
CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and route d with
- typical impedance < 25 mohms
1. 05 V S _V TT
R 5 2 1
1 K _ 1 % _ 0 4
ED P H P D Fu nc ti o n D is ab l e
ED P_ HP D : Pu ll -u p 10 K- D IS A BL ED H PD
Sandy Bridge Processor 1/7 ( DMI,PEG,FDI )
U 4 9 A
B 2 7
20 D M I _ T X N 0 D M I _ R X # [ 0 ]
B 2 5
20 D M I _ T X N 1 D M I _ R X # [ 1 ]
A 2 5
20 D M I _ T X N 2 B 2 4 D M I _ R X # [ 2 ]
20 D M I _ T X N 3 D M I _ R X # [ 3 ]
B 2 8
20 D M I _ T X P 0 B 2 6 D M I _ R X [ 0 ]
20 D M I _ T X P 1 D M I _ R X [ 1 ]
A 2 4
20 D M I _ T X P 2 D M I _ R X [ 2 ]
B 2 3
20 D M I _ T X P 3 D M I _ R X [ 3 ]
G 2 1
20 D M I _ R X N 0
D M I _ T X# [ 0 ]
E 2 2
20 D M I _ R X N 1
F 2 1 D M I _ T X# [ 1 ]
20 D M I _ R X N 2 D M I _ T X# [ 2 ]
D 2 1
20 D M I _ R X N 3
D M I _ T X# [ 3 ]
G 2 2
20 D M I _ R X P 0 D M I _ T X[ 0]
D 2 2
20 D M I _ R X P 1
D M I _ T X[ 1]
F 2 0
20 D M I _ R X P 2
C 2 1 D M I _ T X[ 2]
20 D M I _ R X P 3 D M I _ T X[ 3]
A 2 1
20 F D I _ T X N 0 F D I 0_ T X # [ 0 ]
H 1 9
20 F D I _ T X N 1 F D I 0_ T X # [ 1 ]
E 1 9
20 F D I _ T X N 2
F D I 0_ T X # [ 2 ]
F 1 8
20 F D I _ T X N 3 F D I 0_ T X # [ 3 ]
B 2 1
20 F D I _ T X N 4 F D I 1_ T X # [ 0 ]
C 2 0
20 F D I _ T X N 5
F D I 1_ T X # [ 1 ]
D 1 8
20 F D I _ T X N 6 F D I 1_ T X # [ 2 ]
E 1 7
20 F D I _ T X N 7 F D I 1_ T X # [ 3 ]
A 2 2
20 F D I _ T X P 0 F D I 0_ T X [ 0 ]
G 1 9
20 F D I _ T X P 1
F D I 0_ T X [ 1 ]
E 2 0
20 F D I _ T X P 2 F D I 0_ T X [ 2 ]
G 1 8
20 F D I _ T X P 3 F D I 0_ T X [ 3 ]
B 2 0
20 F D I _ T X P 4
F D I 1_ T X [ 0 ]
C 1 9
20 F D I _ T X P 5 F D I 1_ T X [ 1 ]
D 1 9
20 F D I _ T X P 6 F D I 1_ T X [ 2 ]
F 1 7
20 F D I _ T X P 7
F D I 1_ T X [ 3 ]
1 . 0 5 V S _ V T T J 1 8
20 F D I _ F S Y N C 0 F D I 0_ F S Y N C
J 1 7
20 F D I _ F S Y N C 1 F D I 1_ F S Y N C
H 2 0
20 F D I _ I N T F D I _I N T
J 1 9
20 F D I _ LS Y N C 0 F D I 0_ L S Y N C
H 1 7
R 5 1 9
20 F D I _ LS Y N C 1 F D I 1_ L S Y N C
2 4 . 9_ 1 % _ 0 4
E D P _ C OM P I O A 1 8
e D P _ C OM P I O
A 1 7
DP Compensation Signal
e D P _ I C OM P O
E D P _ H P D B 1 6
e D P _ H P D
C 1 5
11 D P _ A U X _ P
e D P _ A U X
D 1 5
11 D P _ A U X _ N e D P _ A U X #
C 1 7
11 D P _ T X P _ 0 e D P _ T X [ 0 ]
F 1 6
11 D P _ T X P _ 1 e D P _ T X [ 1 ]
C 1 6
11 D P _ T X P _ 2
e D P _ T X [ 2 ]
G 1 5
e D P _ T X [ 3 ]
C 1 8
11 D P _ T X N _ 0
e D P _ T X # [ 0 ]
E 1 6
11 D P _ T X N _ 1 e D P _ T X # [ 1 ]
D 1 6
11 D P _ T X N _ 2 e D P _ T X # [ 2 ]
F 1 5
e D P _ T X # [ 3 ]
P Z 9 8 8 2 7- 36 4 B -0 1 F
3 , 8, 11 , 1 2 , 1 6 , 1 8, 19 , 2 0 , 2 2 , 2 3, 24 , 2 5 , 2 7 , 2 8, 29 , 3 0 , 3 3 , 3 5, 37 , 3 8 , 3 9
1 . 05 V S _ V T T
20 mil
J 2 2 P E G_ I R C O M P _ R
R 1 3 3 2 4 . 9 _ 1% _ 0 4
P E G _ I C O MP I
J 2 1
P E G_ I C OM P O H 2 2
P E G _ R C OM P O
K 3 3
P E G_ R X# 0 1 2
P E G _ R X # [ 0 ]
M 3 5
P E G_ R X# 1 1 2
P E G _ R X # [ 1 ]
L 3 4
P E G_ R X# 2 1 2
P E G _ R X # [ 2 ] J 3 5
P E G_ R X# 3 1 2
P E G _ R X # [ 3 ]
J 3 2
P E G_ R X# 4 1 2
P E G _ R X # [ 4 ]
H 3 4
P E G_ R X# 5 1 2
P E G _ R X # [ 5 ] H 3 1
P E G_ R X# 6 1 2
P E G _ R X # [ 6 ]
G 3 3
P E G_ R X# 7 1 2
P E G _ R X # [ 7 ]
G 3 0
P E G _ R X # [ 8 ] F 3 5
P E G _ R X # [ 9 ]
E 3 4
P E G _ R X # [ 1 0 ]
E 3 2
P E G _ R X # [ 1 1 ] D 3 3
P E G _ R X # [ 1 2 ]
D 3 1
PEG Compensation Signal
P E G _ R X # [ 1 3 ]
B 3 3
P E G _ R X # [ 1 4 ] C 3 2
P E G _ R X # [ 1 5 ]
CAD NOTE: PEG_ICOMPI and RCOMPO signals
J 3 3
P E G _R X [ 0 ] P E G_ R X0 1 2 should be shorted and routed with
L 3 5
P E G_ R X1 1 2
P E G _R X [ 1 ]
K 3 4
P E G_ R X2 1 2 - max length = 500 mils
P E G _R X [ 2 ]
H 3 5
P E G _R X [ 3 ] P E G_ R X3 1 2
H 3 2 - typical impedance = 43 mohms
P E G_ R X4 1 2
P E G _R X [ 4 ]
G 3 4
P E G_ R X5 1 2 PEG_ICOMPO signals should be routed with
P E G _R X [ 5 ]
G 3 1
P E G _R X [ 6 ] P E G_ R X6 1 2
F 3 3
- max length = 500 mils
P E G_ R X7 1 2
P E G _R X [ 7 ]
F 3 0
P E G _R X [ 8 ] - typical impedance = 14.5 mohms
E 3 5
P E G _R X [ 9 ]
E 3 3
P E G _ R X [ 1 0 ]
F 3 2
P E G _ R X [ 1 1 ]
D 3 4
P E G _ R X [ 1 2 ]
E 3 1
P E G _ R X [ 1 3 ]
C 3 3
P E G _ R X [ 1 4 ]
B 3 2
P E G _ R X [ 1 5 ]
M 2 9 P E G_ T X # _0
C 5 9 1 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X #0 1 2
P E G_ T X # [ 0 ]
M 3 2 P E G_ T X # _1 C 5 8 9 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X # [ 1 ] P E G_ T X #1 1 2
M 3 1
P E G_ T X # _2 C 5 9 4 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X # [ 2 ] P E G_ T X #2 1 2
L 3 2 P E G_ T X # _3
C 5 9 6 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X #3 1 2
P E G_ T X # [ 3 ]
L 2 9 P E G_ T X # _4 C 5 9 8 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X # [ 4 ] P E G_ T X #4 1 2
K 3 1
P E G_ T X # _5 C 6 0 1 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X # [ 5 ] P E G_ T X #5 1 2
K 2 8 P E G_ T X # _6
C 6 0 6 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X #6 1 2
P E G_ T X # [ 6 ]
J 3 0 P E G_ T X # _7 C 6 0 8 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X # [ 7 ] P E G_ T X #7 1 2
J 2 8
P E G_ T X # [ 8 ]
H 2 9
P E G_ T X # [ 9 ]
G 2 7
P E G _T X # [ 1 0 ]
E 2 9
P E G _T X # [ 1 1 ]
F 2 7
P E G _T X # [ 1 2 ]
D 2 8
P E G _T X # [ 1 3 ]
F 2 6
P E G _T X # [ 1 4 ]
E 2 5
P E G _T X # [ 1 5 ]
M 2 8
P E G_ T X _ 0 C 5 8 7 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X [ 0 ] P E G_ T X 0 1 2
M 3 3 P E G_ T X _ 1
C 5 8 8 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X 1 1 2
P E G_ T X [ 1 ]
M 3 0 P E G_ T X _ 2 C 5 9 3 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X [ 2 ] P E G_ T X 2 1 2
L 3 1
P E G_ T X _ 3 C 5 9 5 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X [ 3 ] P E G_ T X 3 1 2
L 2 8 P E G_ T X _ 4
C 5 9 7 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X 4 1 2
P E G_ T X [ 4 ]
K 3 0 P E G_ T X _ 5 C 6 0 2 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X [ 5 ] P E G_ T X 5 1 2
K 2 7
P E G_ T X _ 6 C 6 0 4 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X [ 6 ] P E G_ T X 6 1 2
J 2 9 P E G_ T X _ 7
C 6 0 7 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X 7 1 2
P E G_ T X [ 7 ]
J 2 7
P E G_ T X [ 8 ]
H 2 8
P E G_ T X [ 9 ]
G 2 8
P E G_ T X [ 1 0 ]
E 2 8
P E G_ T X [ 1 1 ]
F 2 8
P E G_ T X [ 1 2 ] Q 2 6
D 2 7
SC70-5 & SC70-3
P E G_ T X [ 1 3 ]
E 2 6 5 1
P E G_ T X [ 1 4 ] G N D N C
D 2 5 2
Co-lay
P E G_ T X [ 1 5 ] GN D
4 3
V C C V O
3 . 3 V
* T MP 2 0
Q 2 7
2 1
1:2 ( 4m il s:8 mi ls )
V C C O U T
C 6 7 3
3
C 6 7 2
G N D
0 . 1u _ 1 0 V _ X 7R _ 0 4 0 . 1 u_ 1 0 V _ X 7R _ 0 4
G 71 1 S T 9 U
PLACE NEAR U3
3 , 5 , 2 3 , 2 4, 25 , 3 5 , 3 9 1 . 0 5V S _ V T T
3 . 3 V
Schematic Diagrams
Sheet 2 of 49
Sandy Bridge
Processor 1/7
T H E R M _V OL T 3 4
8/30
1
3
2
Sandy Bridge Processor 1/7 B - 3