Sandy Bridge Processor 2/7 - Clevo W150HRM Service Manual

Table of Contents

Advertisement

Schematic Diagrams

Sandy Bridge Processor 2/7

PU/PD for JTAG signals
1. 0 5 V S _ V T T
3 . 3V S
I f PR OC HO T# is n ot u se d,
t he n it m us t b e te rm in at ed
w it h a 56 -O +- 5% p ul l- up
r es is to r to 1. 05 VS _V TT .
Sheet 3 of 49
Sandy Bridge
Processor 2/7
Buffered reset to CPU
1 2 , 22 , 2 8
P L T _R S T #
B - 4 Sandy Bridge Processor 2/7
Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG )
5 1_ 0 4
R 5 1 0
XD P _ TM S
5 1_ 0 4
R 5 0 6
XD P _ TD I _ R
* 5 1_ 0 4
R 5 0 8
XD P _ P R E Q #
XD P _ TD O_ R
5 1_ 0 4
R 5 1 1
5 1_ 0 4
R 5 1 3
XD P _ TC L K
XD P _ TR S T #
5 1_ 0 4
R 5 0 5
H _S N B _ I V B #
2 3
H _ S N B _ I V B #
R 4 94
1 K _0 4
X D P _D B R _R
H _C A T E R R #
2 3, 3 4
H _ P E C I
H _ P R OC H O T#
R 1 0 9
56 _ 1 % _0 4
H _ P R O C H OT # _ D
3 9
H _ P R O C H OT #
2 3
H _ TH R M T R I P #
2 0
H _ P M_ S Y N C
R 4 9 8
*1 0 mi l _ sh o rt
H _ C P U P W R GD _R
2 3
H _ C P U P W R GD
P M S Y S _P W R G D _ B U F
R 1 7 4
13 0 _ 1% _ 0 4
V D D P W R G OO D _ R
1 . 05 V S _ V T T
B U F _ C P U _ R S T #
3 . 3 V S
R 5 1 2
7 5_ 0 4
R 6 58
B U F _ C P U _ R S T#
R 5 1 5
4 3 . 2_ 1 % _0 4
1 0K _0 4
D
Q 3 7B
5
G
M T D N 7 0 0 2 Z H S 6 R
S
D
2
G
Q 37 A
S
M TD N 7 0 0 2Z H S 6 R
3 4
R 5 1 8
*1 . 5 K _ 1% _ 0 4
R 52 4
C 6 21
R 51 7
10 0 K _ 0 4
6 8 p _5 0 V _ N P O _ 04
* 75 0 _ 1% _ 0 4
U 49 B
A 2 8
B C LK
C 2 6
A 2 7
P R OC _S E LE C T #
B C L K #
A N 3 4
S K T OC C #
A 1 6
D P L L _R E F _ S S C LK
A 1 5
D P L L _ R E F _ S S C L K #
A L 3 3
C A TE R R #
A N 3 3
R 8
C P U D R A M R S T #
P E C I
S M_ D R A MR S T #
A L 3 2
A K 1
S M _ R C O MP _0
P R OC H OT #
S M _ R C OM P [ 0]
A 5
S M _ R C O MP _1
S M _ R C OM P [ 1]
A 4
S M _ R C O MP _2
S M _ R C OM P [ 2]
A N 3 2
T H E R MT R I P #
A P 2 9
X D P _P R D Y #
P R D Y #
A P 2 7
X D P _P R E Q#
P R E Q #
A R 2 6
X D P _T C LK
T C K
A R 2 7
X D P _T M S
T MS
A M3 4
A P 3 0
X D P _T R S T#
P M _S Y N C
TR S T #
A R 2 8
X D P _T D I _R
T D I
A P 2 6
X D P _T D O_ R
A P 3 3
T D O
U N C O R E P W R G OO D
A L 35
X D P _D B R _ R
V 8
D B R #
S M _D R A M P W R OK
A T 28
X D P _B P M0 _ R
B P M # [ 0]
A R 2 9
X D P _B P M1 _ R
B P M # [ 1]
A R 3 0
X D P _B P M2 _ R
B P M # [ 2]
A R 3 3
A T 30
X D P _B P M3 _ R
R E S E T #
B P M # [ 3]
A P 3 2
X D P _B P M4 _ R
B P M # [ 4]
A R 3 1
X D P _B P M5 _ R
B P M # [ 5]
A T 31
X D P _B P M6 _ R
B P M # [ 6]
A R 3 2
X D P _B P M7 _ R
B P M # [ 7]
P Z 9 8 8 2 7-3 6 4 B -0 1F
H _ P R O C H OT #
Q1 6
G
C 6 2 2
H _ P R OC H OT # _ E C
MT N 7 0 0 2 Z H S 3
R 20 3
47 p _ 50 V _ N P O_ 0 4
1 0 0K _ 0 4
CAD Not e: C apaci tor need to b e pl aced
clo se t o bu ffer outp ut p in
2 , 8 , 1 1 , 12 , 1 6 , 1 8, 1 9 , 2 0 , 22 , 2 3 , 2 4, 2 5 , 2 7 , 28 , 2 9 , 3 0, 3 3 , 3 5, 37 , 3 8 , 3 9
9 , 1 0, 1 1 , 1 2, 18 , 1 9 , 20 , 2 1 , 2 2, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 2 , 3 3, 3 4 , 3 5 , 39
Processor Pullups/Pull downs
H _ P R O C H OT #
R 1 1 0
H _ C P U P W R GD _ R
R 4 9 9
TRA CE WI DTH 10MI L, LE NGTH <50 0MIL S
C L K _ E X P _ P 1 9
C L K _ E X P _ N 1 9
C L K _ D P _ P 1 9
DDR3 Compensation Signals
C L K _ D P _ N
19
S M_ R C OM P _ 0
R 5 3 1
S M_ R C OM P _ 1
R 5 2 8
S M_ R C OM P _ 2
R 5 2 9
S3 circuit:- DRAM PWR GOOD logic
3 . 3V
3 . 3 V
C 2 78
R 1 87
R 1 8 8
1 . 5 V S _ C P U
1
2 0
P M _D R A M_ P W R GD
4
P MS Y S _ P W R G D _ B U F
2
2 0, 3 7
1 . 8 V S _ P W R G D
U 1 4
* MC 7 4V H C 1 G 08 D F T 1G
R 1 8 6
0 _ 0 4
Q 13
G
3 5 , 3 7, 38
S U S B
* MT N 7 0 0 2Z H S 3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1 . 5 V
R 2 30
R 2 3 1
* 0 _0 4
1 K _ 0 4
Q1 7
MT N 7 0 0 2 Z H S 3
C P U D R A MR S T #
S
D
R 2 3 5
1 K _ 04
D R A M R S T _ C N T R L 8 , 1 9
R 22 5
C 3 1 5
4 . 9 9 K _1 % _ 0 4
0 . 0 47 u _ 10 V _ X 7 R _ 0 4
6 , 8 , 9 , 1 0, 2 5 , 2 9 , 35 , 3 7 , 3 8
1 . 5 V
6 , 3 5 , 3 8
1 . 5 V S _ C P U
2 , 5 , 2 3 , 24 , 2 5 , 3 5, 3 9
1 . 0 5V S _V TT
3 . 3 V
3 . 3 V S
1 . 0 5 V S _ V T T
62 _ 0 4
10 K _ 0 4
14 0 _ 1 %_ 0 4
25 . 5 _ 1 %_ 0 4
20 0 _ 1 %_ 0 4
R 17 5
2 0 0 _1 % _ 04
R 16 8
* 39 _ 0 4
D D R 3 _ D R A MR S T # 9 , 1 0

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

W150hrq

Table of Contents