Table 4-4. Memory Controller Initialization For 100(50) Mhz - Motorola MSC8101 ADS User Manual

TABLE 4-4. Memory Controller Initialization for 100(50)
Reg. Device Type
BR0 SM73228XG1JHBG0 by
Smart Modular Tech.
SM73248XG2JHBG0 by
Smart Modular Tech.
SM73288XG4JHBG0 by
Smart Modular Tech.
OR0 SM73228XG1JHBG0 by
Smart Modular Tech.
SM73248XG2JHBG0 by
Smart Modular Tech.
SM73288XG4JHBG0 by
Smart Modular Tech.
BR1
BCSR0-3
OR1
BR2 SDRAM 64bit Supported
OR2 MT48LC2M32B2T6-8x2
by Micron
b
BR2 SDRAM 32bit Supported
b
OR2 MT48LC2M32B2T6-8 by
Micron
c
BR3 SDRAM 32bit Supported
c
OR3 MT48LC2M32B2T6-8 by
Micron
BR4 QFALC - 4ch. T1/E1
OR4
36
Freescale Semiconductor, Inc.
Operating Instructions
Warning
The initialization in TABLE 4-4. "Memory Control-
ler Initialization for 100(50) MHz" below
on design and are not verified yet, due to silicon
availability problems.
Init Value
Bus
[hex]
FF801801
FF001801
FE001801
Buffered
PPC
FF800866
(FF800836)
FF000866
(FF000836)
FE000866
(FE000836)
Buffered 14501801
PPC
FFFF8010
(FFFF8020)
Non-buffered 20000041
PPC
FF003080
Non-buffered 20001841
PPC with
Host support
FF803280
Non-buffered 20801841
PPC with
Host support
FF803280
Buffered 146088A1
PPC
FFFF8106
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are based
a
MHz
Description
Base at FF800000, 32 bit port size, no parity,
GPCM
Base at FF00000, 32 bit port size, no parity,
GPCM
Base at FE00000, 32 bit port size, no parity,
GPCM
8MByte block size, CS early negate, 12(6) w.s.,
Timing relax
16MByte block size, CS early negate, 12(6) w.s.,
Timing relax
32MByte block size, CS early negate, 12(6) w.s.,
Timing relax
Base at 14500000, 32 bit port size, no parity,
GPCM
32 KByte block size, all types access, 1 w.s.
(32 KByte block size, all types access, 2 w.s.)
Base at 20000000, 64 bit port size, no parity,
SDRAM machine 1
16MByte block size, 4 banks per device, row starts
at A8, 11 row lines, internal bank interleaving
allowed
Base at 20000000, 32 bit port size, no parity,
SDRAM machine 1
8MByte block size, 4 banks per device, row starts
at A9, 11 row lines, internal bank interleaving
allowed
Base at 20800000, 32 bit port size, no parity,
SDRAM machine 1
8MByte block size, 4 banks per device, row starts
at A9, 11 row lines, internal bank interleaving
allowed
Base at 14608000, 8 bit port size, no parity, UPMB
on PPC bus
32K Byte block size, burst inhibit, eight idle cycle
are inserted before next access
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