Pll Circuits - Icom IC-7800 Service Manual Addendum

The antenna switching relays are controlled by the RL-CTRL
CPU (IC11, pins 6, 9, 12, 15) as the "ANT1A", "ANT2A",
"ANT3A" and "ANT4A" signals respectively.
3-2-11 ALC CIRCUIT
(CTRL BOARD, LOGIC AND MAIN UNITS)
The ALC (Automatic Level Control) circuit controls the gain
of IF amplifiers in order for the IC-7800 to output a constant
RF power set by [RF PWR] control even when the supplied
voltage shifts, etc.
The RF power level is detected at one of the SWR detector
circuits (CTRL board; D102) to be converted into DC voltage
and applied to the MAIN unit as the FORV signal via the
LOGIC unit.
The FORV signal from the LOGIC unit is applied to the com-
parator (MAIN unit; IC60, pin 2). The POCV signal, con-
trolled by [RF POWER] control via the I/O expander (MAIN
unit; IC330, pin 4), is also applied to the other input (pin 3)
for reference. The compared signal is output from pin 1 and
applied to the IF amplifiers (MAIN unit; Q504, Q506) to con-
trol amplifying gain.
When the FORV signal exceeds the POCV voltage, ALC
bias voltage from the comparator controls the IF amplifiers.
This adjusts the output power to a specified level from
[RF POWER] control until the FORV and POCV voltages are
equalized.
In AM mode, the comparator operates as an averaging ALC
amplifier. Q61 (MAIN unit) turns ON and shift the POCV volt-
age to adjust the TX output power for 50 W (maximum)
through R82.
The ALC bias voltage is also applied to the ALC meter ampli-
fier (MAIN unit; IC61, pin 9) to obtain an ALC meter signal
(ALCL). The amplified signal is applied to the main CPU2
(LOGIC unit; IC604, pin 115) to drive the S/RF meter via the
front CPU (IC6) on the DISPLAY board.
An external ALC input from [ALC] jack, [ACC1] or [ACC2]
sockets is applied to the ALC amplifier (Q62). External ALC
operation is identical to that of the internal ALC.
The FORV signal is also applied to the power meter amplifi-
er (LOGIC unit; IC851, pin 5). The amplified signal is applied
to the main CPU2 (LOGIC unit; IC604, pin 113) to drive the
S/RF meter as an FORL signal when the power meter is
selected.
3-2-12 APC CIRCUIT
(MAIN UNIT, CTRL AND PA200W BOARDS)
The APC (Automatic Power Control) circuit protects the
power amplifiers on the PA 200W board from high SWR and
excessive current.
The reflected wave signal appears and increases when the
connected antenna is mismatched to 50 Ω. The SWR detec-
tor (CTRL board; D101) detects the reflected signal, and
applies it to the APC circuit (MAIN unit; IC60, pin 13) as a
REFV signal via the LOGIC unit.
When the REFV signal level increases, the APC circuit
decreases the ALC voltage to activate the APC.
For the current APC, the power transistor current is obtained
by detecting the voltages (IDH and IDL) which appear at
both terminals of the ID detector (PA200W board;
R521–R523). The detected voltages are applied to the dif-
ferential amplifier (IC60, pins 5, 6). When the current of tran-
sistors is increased, the amplifier controls the ALC line to
prevent excessive current flow.
3-2-13 TEMPERATURE PROTECTION CIRCUIT
(PA200W BOARD)
The cooling fan (CHASSIS; MF1) is activated while trans-
mitting or when the temperature of the power amplifier
exceeds the preset value. The temperature protection circuit
consists of IC604, IC330, IC821, Q821, Q822 and R3.
While transmitting, IC821 and Q821 are turned ON, and pro-
vide a voltage to the cooling fan to rotate at medium speed.
The thermistor (R3) detects the temperature of the power
amplifiers (Q401, Q402). The detected signal is applied to
the CPU (IC604, pin 118) to analyze the power amplifier's
temperature via "THML" signal. The signal is applied to the
D/A converter (IC330), and is then applied to the FAN con-
troller (IC821, pin 1, Q821, Q822) via "FANI" signal. The
control signal outputs from the controller (IC821, pin 7) as
"FANV" signal, and then controls cooling fan via the J824.

3-3 PLL CIRCUITS

3-3-1 GENERAL
The PLL circuits consist of OSC, RXPLL-A and RXPLL-B
units.
The OSC unit oscillates 10 MHz reference frequency for
RXPLL-A, RXPLL-B units and external reference frequency.
The RXPLL-A unit oscillates 6 LO frequencies for the RX-A
unit's receive 1st and 2nd LO frequencies, MAIN unit's
transmit 1st, 2nd and 3rd LO frequencies, marker frequency.
The RXPLL-B unit oscillates 6 LO frequencies for the RX-B
unit's receive 1st and 2nd LO frequencies, SCOPE unit's ref-
erence frequency, clock signal of DSP-TX, DSP-A and DSP-
B board.
1st and 2nd LO frequency lists for RX, 3rd IF and LO fre-
quency lists and 2nd IF and LO frequency list are shown at
page 3-28.
1st IF and 1st LO frequency lists for TX are shown at page
3-29.
3-3-2 OSCILLATOR CIRCUIT (OSC UNIT)
The reference oscillator (IC91, X1) generates a 10 MHz fre-
quency which field intensity is 0 dBm. The signal is used for
the RXPLL-A and RXPLL-B unit's system clock, etc.
• IN CASE OF USING AS RXPLL-A AND RXPLL-B UNIT'S
SYSTEM CLOCK
The oscillated signal is amplified at the buffer amplifier
(Q21), and is the applied to the amplifier (Q22). The ampli-
fied signal passes through the oscillated signal selector
(RL11), and is then amplified at the buffer amplifier (Q70).
The amplified signal is applied to the RXPLL-A and RXPLL-
B units via the J72 and J73, respectively.
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