Port Allocations - Icom IC-7800 Service Manual Addendum

3-7 PORT ALLOCATIONS

3-7-1 MAIN CPU2 PORT ALLOCATIONS
(LOGIC UNIT; IC604)
Pin Port
number name
5–9 H8_A0–A4
11–17 H8_A5–A11 Output address bus signals.
19, 20 H8–A12, A13
Input port for the PLL unlock signal
21 UNLKA
from the RXPLL-A unit.
Input port for the PLL unlock signal
22 UNLKB
from the RXPLL-B unit.
23 ECK Outputs clock signal to the EEPROM.
I/O port for the data signal from/to the
24 EDT
EEPROM.
Outputs clock signal to the EEPROM
26 DSCLA
on the DIGISEL-A unit.
I/O port for the data signal from/to the
27 DSDAA
EEPROM on the DIGISEL-A unit.
Outputs clock signal to the EEPROM
28 DSCLB
on the DIGISEL-B unit.
I/O port for the data signal from/to the
29 DSDAB
EEPROM on the DIGISEL-B unit.
30 RTKI Input port for the RTTY keying signal.
Input port for the transverter control
signal from ACC jack on the rear
31 TRVI
panel.
Outputs data signals to the DDS, PLL
33 SDAT
and DSP ICs on the SCOPE unit.
Outputs strobe signal to the PLL IC on
34 SST2
the SCOPE unit.
Outputs external SEND relay (lead
type) control signal.
35 EXRL1
High : The relay switches ON.
Outputs external SEND relay (semi-
conductor type) control signal.
36 EXRL2
High : The relay switches ON.
Outputs clock signal to the RXPLL-
42 PCK/CON0
A/B ICs .
Outputs data signal to the RXPLL-A/B
43 PDAT/CON1
ICs.
Outputs strobe select signal to the
46 PSLA
PLL-A IC.
Outputs strobe signal to the RXPLL-A
47 PSTA
IC.
Outputs strobe select signal to the
48 PSLB
PLL-B IC.
Outputs strobe signal to the RXPLL-B
49 PSTB
IC.
Outputs clock signal to the ICs (other
51 MCK
than PLL, scope and DSP ICs).
Outputs data signal to the ICs (other
52 DAT
than PLL, scope and DSP ICs).
54 CTXD Output port for the CI-V data.
Input port for the CI-V data and CI-V
55 CRXD/CBSY
bus busy signals.
Description
Pin Port
number name
56 DSPCK
57 DSPR
58 ISTA
59 SST1
60 SPS0
61 SCK
63–69, 71, H8_D0–
73–80 H8_D15
81 MUTI
82 TXS
83 NSQA
85 TRAS
104 NSQB
105 RXSA
106 RXSB
107 SQSA
108 SQSB
109 SQLSM
110 SQLSS
113 FORL
114 REFL
115 ALCL
116 IDL
117 VDL
118 THML
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Description
Outputs clock signal to the DSP IC.
Outputs data signal to the DSP IC.
Outputs start signal to the internal
antenna tuner.
Outputs chip select signal to the DDS
IC on the SCOPE unit.
Outputs profile select signal to the
DDS IC on the SCOPE unit.
Outputs clock signals to the DDS, PLL
and DSP ICs on the SCOPE unit.
I/O port for data bus signals.
Input port for the external mute control
signal.
High : Mute ON.
Outputs control signal to the TX circuit
power supply.
Low : While transmitting.
Input port for the noise pulse signal
from the RX-A circuit.
Outputs control signal for transmisson
(other than PTT and the control signal
from ACC).
Input port for the noise pulse signal
from the RX-B circuit.
Outputs control signal to the RX-A cir-
cuit power supply.
Low : While the RX-A circuit is acti-
vated.
Outputs control signal to the RX-B cir-
cuit power supply.
Low : While the RX-B circuit is acti-
vated.
Outputs RX-A circuit squelch control
signal to the ACC jack.
High : RX LED lights ON.
Outputs RX-B circuit squelch control
signal to the ACC jack.
High : RX LED lights ON.
Outputs AF mute control signal to the
MAIN RX circuit.
Low : Squelch is open.
Outputs AF mute control signal to the
SUB RX circuit.
Low : Squelch is open.
Input port for the "FOR" signal.
Input port for the "REF" signal.
Input port for the ALC meter control
signal.
Input port for the ID meter control sig-
nal.
Input port for the VD meter control sig-
nal.
Input port for the PA unit temperature
detect signal.