Integra DTR-4.9 Service Manual page 64

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-29
Q8051 : SiI9013 ( HDMI Receiver)-4/4
TERMINAL DESCRIPTION
Configuration / Programming Pins
Pin Name
INT
RESET#
DSCL
DSDA
CSCL
CSDA
SCDT
CI2CA
PWR5V
RSVDL
RSVD
NC
Differential Signal Data Pins
Pin Name
RXC+
RXC-
TE
L 13942296513 RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
Power and Ground Pins
Pin Name
CVCC18
CGND
IOVCC
IOGND
AVCC
AGND
PVCC
PGND
AUDPVCC18
AUDPGND
DVCC18
DGND
XTALVCC
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Pin # Dir Description
91 Output Interrupt Output.
89 Input Reset Pin. Active LOW. Note that this pin must be dynamically controlled as
part of normal operation. This is typically done by the host processor.
2
42 Input DDCI C Clock for DDC.
2
41 Bi-Di DDCI C Clock for DDC.
40 Input Configuration I C Clock.
39 Bi-Di Configuration I C Data.
90 Output Indicates active video at HDMI input port.
2
38 Input I C Device Address Select.
44 Input TMDS Port Transmitter Detect.
88 Input Reserved, must be tied LOW.
48 --- Reserved Pin, leave unconnected.
43 --- No connect.
Pin # Dir Description
51 Input TMDS input clock pair.
50 Input
55 Input TMDS input data pair.
54 Input
59 Input TMDS input data pair.
58 Input
63 Input TMDS input data pair.
62 Input
Pin #
12, 24, 36, 45, 81, 112, 125
13, 25, 37, 80, 113, 126
7, 19, 31, 68, 77, 98, 107, 120
6, 18, 30, 69, 78, 97, 106, 118
49, 53, 57, 61
52, 56, 60, 64
47
46
82
83
66
65
86
87
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Type Description
Power Digital Logic VCC (1.8V)
Ground Digital Logic GND
Power Input / Output Pin VCC (3.3V)
Ground Input / Output Pin GND
Power TMDS Analog VCC (3.3V)
Ground TMDS Analog GND
Power TMDS PLL VCC (3.3V)
Ground TMDS PLL GND
Power ACR PLL VCC (1.8V)
Ground ACR PLL GND
Power ACR PLL Digital VCC (1.8V)
Ground ACR PLL GND
Power ACR PLL Crystal Input VCC (3.3V)
Power ACR PLL Regulator VCC (3.3V)
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DTR-4.9
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