Integra DTR-4.9 Service Manual page 63

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-28
Q8051 : SiI9013 ( HDMI Receiver)-3/4
TERMINAL DESCRIPTION
Digital video Output Pins
Pin Name Pin #
QE0 124
QE1 123
QE2 122
QE3 121
QE4 117
QE5 116
QE6 115
QE7 114
QE8 111
QE9 110
QE10 109
QE11 108
QE12 105
QE13 104
QE14 103
QE15 102
QE16 101
QE17 100
QE18 99
TE
L 13942296513
QE19 96
QE20 95
QE21 94
QE22 93
QE23 92
Digital Audio Output Pins
Pin Name
XTALIN
XTALOUT
MCLK
SCK
WS
SD0
SD1
SD2
SD3
www
SPDIF
MUTE
.
http://www.xiaoyu163.com
Dir Description
Output
Output
Output 24-Bit Even Pixel
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pin # Dir Description
85 Input Crystal Clock Input.
84 Output Crystal Clock Output.
79 Bi-Di Audio Master Clock Input Reference.
2
76 Output I S Serial Clock Output.
2
75 Output I S Word Select Output.
2
74 Output I S Serial Data Output.
2
73 Output I S Serial Data Output.
2
72 Output I S Serial Data Output.
2
71 Output I S Serial Data Output.
70 Output S/PDIF Audio Output.
x ao
67 Output Mute Audio Output.
y
i
http://www.xiaoyu163.com
8
Pin Name Pin #
QO0 35
QO1 34
QO2 33
QO3 32
QO4 29
QO5 28
QO6 27
QO7 26
QO8 23
QO9 22
QO10 21
QO11 20
QO12 17
QO13 16
QO14 15
QO15 14
QO16 11
QO17 10
Q Q
QO18 9
3 6 7 1 3
QO19 8
QO20 5
QO21 4
QO22 3
QO23 2
127
DE
HSYNC 128
VSYNC 1
ODCK 119
u163
.
2 9 9 4 2 8
Dir Description
Output
Output
Output 24-Bit Odd Pixel
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
1 5 0 5 8 2 9 9 4
Output
Output
Output
Output
Output
Output Data enable
Output Horizontal Sync.
Output Vertical Sync.
Output Output Data Clock
m
co
DTR-4.9
9 9
2 8 9 9