Integra DTR-4.9 Service Manual page 60

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-25
Q8401 : SiI9034CTU (HDMI Transmitter)-4/4
TERMINAL DESCRIPTION
Configuration / Programming Pins
Pin Name
HPD
RSVDL
INT
Control Pins
Pin Name
CI2CA
RESET#
CSCL
CSDA
DSCL
DSDA
Diffrential Signal Data Pins
Pin Name
TX0+
TX0-
TX1+
TE
L 13942296513
TX1-
TX2+
TX2-
TXC+
TXC-
EXT_SWING
Power and Ground Pins
Pin Name
CVCC18
IOVCC33
RSVD18
AVCC33
AVCC18
AGND
PVCC1
PVCC2
DDCPWR5V
GND
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Pin # Dir Description
51 Input Hot Plug Detect Input.
52 Input Reserved for use by Silicon Image and must be tied LOW.
24 Output Interrupt Output.
Pin # Dir Description
2
50 Input I C device address select
25 Input Reset Pin (Active LOW) 5V Tolerant
2
48 Input I C Clock
2
49 Bi-Di I C Data (Open Drain Output)
46 Bi-Di DDC Clock (Open Drain Output)
47 Bi-Di DDC Data (Open Drain Output)
Pin # Dir Description
34 Output TMDS output data pairs.
33 Output
37 Output
36 Output
40 Output
39 Output
31 Output TMDS output clock pair.
30 Output
27 Input Voltage Swing Adjust. A resistor is tied from this pin to AVCC18.
This resistor determines the amplitude of the voltage swing.
Pin # Type
12, 64, 76, 99 Power
14, 53, 66, 89 Power
55 Power
44 Power
32, 38 Power
26, 29, 35, 41, 43 Ground
28 Power
42 Power
45 Power
13, 54, 65, 67 - 70, Groud
80 - 83, 87, 95 - 98,
100
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8
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Description
Digital Core VCC. Connect to 1.8v supply.
IO Pin VCC. Connect to 3.3V supply.
Reserved. Must be connected to 1.8V for all operations.
Analog VCC. Connect to 3.3V supply.
Analog VCC. Connect to 1.8V supply.
Analog GND.
TMDS Core PLL power. Connect to 1.8V supply.
Filter PLL Power. Connect to 1.8V supply.
Power reference signal. Used to supply power to the DDC I2C pads
when chip is powerd off. Connect to 5V supply.
Digital Ground.
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2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
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DTR-4.9
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