Integra DTR-4.9 Service Manual page 59

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-24
Q8401 : SiI9034CTU (HDMI Transmitter)-3/4
TERMINAL DESCRIPTION
Video and Audio Input pins
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
TE
L 13942296513
D19
D20
D21
D22
D23
IDCK
DE
HSYNC
VSYNC
SCK
WS
SD0
SD1
SD2
SD3
DL0
DR0
DL1
DR1
DL2
DR2
DL3
www
DR3
DCLK
MCLK
.
SPDIF
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Pin # Dir Description
94 Input These are the lower 12 bits of the 24-bit pixel bus.
93 Input These pins are highly configurable, and support multiple RGB and YCbCr formats.
92 Input
91 Input
90 Input
86 Input
85 Input
84 Input
79 Input
78 Input
77 Input
75 Input
74 Input These are the upper 12 bits of the 24-bit pixel bus.
73 Input
72 Input
71 Input
63 Input
62 Input
61 Input
60 Input
59 Input
58 Input
57 Input
56 Input
88 Input Input Data clock
1 Input Data enable
2 Input Horizontal Sync input control signal
3 Input Vertical Sync input control signal
2
11 Input I S Serial Clock
2
10 Input I S Word Select
2
9 Input I S Serial data
2
Input I S Serial data
8
2
7 Input I S Serial data
2
6 Input I S Serial data
17 Input One-bit Audio data Left 0
16 Input One-bit Audio data Right 0
19 Input One-bit Audio data Left 1
18 Input One-bit Audio data Right 1
One-bit Audio data Left 2
21 Input
20 Input One-bit Audio data Right 2
23 Input One-bit Audio data Left 3
22 Input One-bit Audio data Right 3
x ao
15 Input One-bit Audio Clock Input y
5 Input Audio Input Master Clock
i
4 Input S/PDIF Audio Input.
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