Line Status Register - National Instruments GPIB-COM User Manual

Programming the GPIB-COM

Line Status Register

Offset from Base I/O Address = 5
Register Address = XFD
7 6
0
TEMT
The Line Status Register provides information about the status of the data transfer. On the GPIB-
COM this register is implemented as a read-only register. Writing to the line status register will
not change its contents. The function of each bit in this register is explained below.
Bit Mnemonic
7r 0
6r TEMT
5r THRE
4r BI
GPIB-COM User Manual
5 4
THRE BI
Description
Reserved Bit
This bit always reads as 0.
Transmitter Shift Register Empty Bit
This bit is cleared when a character is transferred from the
Transmitter Holding Register to the Transmitter Shift Register
and set when the character has been shifted out of the Shift
Register onto the serial output line.
On the GPIB-COM, there is no shift register so this bit behaves
exactly the same as the THRE bit.
Transmitter Holding Register Empty Bit
This bit is cleared when the processor writes a character into the
Transmitter Holding Register and set when the character has
been transmitted and the INS8250 is ready to send another
character.
This bit functions identically on the GPIB-COM and the
INS8250.
Break Interrupt Bit
This bit is set to logical 1 when the serial data input remains in
the logical 0 state for longer than one full word transmission
time.
On the GPIB-COM, this bit is always clear.
5-12
3 2
PE
FE
© National Instruments Corporation
Section Five
1
0 R
OE DR