Divisor Latch Least Significant Byte (Lsb) Register; Divisor Latch Most Significant Byte (Msb) Register - National Instruments GPIB-COM User Manual

Programming the GPIB-COM

Divisor Latch Least Significant Byte (LSB) Register

Offset from Base I/O Address = 0
Register Address = XF8
DLAB bit in Line Control Register = 1
7 6
DL7
DL6
Bit Mnemonic
7-0r/w DL[7-0]

Divisor Latch Most Significant Byte (MSB) Register

Offset from Base I/O Address = 1
Register Address = XF9
DLAB bit in Line Control Register = 1
7 6
DL15
DL14
The value stored in these two registers is used to determine the baud rate for serial communica-
tions. The 16-bit number formed by the Divisor Latch LSB and MSB is divided into a 1.8432
MHz clock to produce the baud rate.
The Divisor Latch Registers are ignored by the GPIB-COM circuitry; however, they are available
on the GPIB-COM and can be written to and read by software.
Bit Mnemonic
7-0r/w DL[15-8]
GPIB-COM User Manual
5 4
DL5 DL4
Description
Data Bits 7 through 0
5 4
DL13 DL12
Description
Data Bits 15 through 8
5-4
3 2
DL2
DL3
3 2
DL10
DL11
© National Instruments Corporation
Section Five
1
0
DL1 DL0 R/W
1
0
DL9 DL8 R/W