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Programming
In read mode, data is available for reading when the DRDY bit is set. The program waits until
the DRDY bit is set, then reads the data from the enabled port. Each time the DRDY bit is set,
another data value has been latched and can be read.
To perform read-programmed I/O transfers, follow these steps:
1. Write hex 0600 to the CFG1 Register to set up the handshaking mode.
2. Wait until DRDY1 becomes set (poll the STAT Register).
3. Read the 16-bit data from Port A.
4. Wait until DRDY1 becomes set, then read the next data value from Port A.
5. Repeat step 4 until all data has been read from Port A.
The digital I/O connector has two extra input lines and two extra output lines. The status of the
input lines IN1 and IN2 can be read from the STAT Register. The output lines OUT1 and OUT2
are controlled by bits in the CFG1 and CFG2 Registers. These lines are useful for reading and
sending status or control information needed in addition to the handshaking lines. These extra
lines are independent of the group designations.
Input Data Latch
When an I/O port is configured as an input port (read mode) and the corresponding DBLBUF bit
is cleared, reading the port returns the current data on the I/O lines, whether or not handshaking
is enabled.
When an I/O port is configured as a double-buffered input port, that is, the corresponding
DBLBUF bit is set, and the handshaking is enabled, the REQ signal latches the data into the port.
•
Level Mode–In either the active high or active low level mode, data is latched into the port
on the leading edge of REQ until the REQ is inactive.
•
Pulse Mode–The active edge (leading edge or trailing edge) of REQ latches data into the
port, until the data in the input buffer is read.
Interrupt Handling
Five conditions can generate an interrupt: DRDY1 set, DRDY2 set, Group 1 DMA terminal
count received, Group 2 DMA terminal count received, and a rising edge on Counter 3 received.
Each of these conditions has an interrupt enable bit in a CFG Register and an interrupt status bit
in the STAT Register. The interrupt condition is enabled to generate interrupts by setting the
appropriate enable bit in the CFG Registers. When the interrupt service routine is entered, the
appropriate status bits of the STAT Register reflect which interrupt requests are active. When
the interrupt condition has been serviced, writing to an interrupt clear register may be necessary
to clear the interrupt status bit. Table 4-3 lists all of the interrupt conditions and status.
AT-DIO-32F User Manual
4-44
© National Instruments Corporation
Chapter 4
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