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A
PCIE3.3VCC
4
P1
B1
+12V
B2
+12V
B3
RSVD
B4
GND
B5
SMCLK
B6
SMDAT
B7
GND
B8
+3.3V
B9
JTAG1
B10
3.3Vaux
B11
WAKE#
C1
0.1uF
B12
RSVD
B13
GND
B14
PETp0
B15
PETn0
B16
GND
B17
PRSNT2#
B18
GND
PCI Express x1 Edge
3
PCIE3.3VCC
U3
250mA Max.
1
5
VIN
VOUT
C5
3
C6
1uF 10V
ON/OFF
10uF 10V
2
4
GND
BYPASS
C7
LP2992
0.01uF
PLACE CLOSE TO 8311!
PLL Filter
2
FB1
1
2
C12
C13
C14
+
.1uF
.01uF
47uF 10V
C15 1uF 10V
8311_1.5V
PCIE12VCC
C17
C25
C26
C27
C28
0.1uF
+
10uF 16V
0.1uF
0.1uF
0.1uF
Place close to the
8311_3.3V
edge connector
PCIE3.3VCC
C29
1
0.1uF
C37
C38
C39
10uF 10V
10uF 10V
10uF 10V
8311_1.5V
Place one cap. to
each
edge
connector's
C40
3.3V pin.
0.1uF
A
B
PCIE12VCC
PCIE3.3VCC
PRSNT
A1
PRSNT1#
A2
PCIE3.3VCC
+12V
A3
+12V
A4
GND
A5
R6
1K
WAKEIN#
JTAG2
ROOT_COMPLEX#
A6
R3
1K
JTAG3
A7
JTAG4
A8
TP1
JTAG5
A9
R8
+3.3V
A10
R9
+3.3V
A11
PERST#
R10
PERST#
R11
R12
10K
A12
D1
BAT54/SOT
GND
A13
REFCLK+
A14
REFCLK-
A15
GND
A16
1
2
PERp0
A17
PERn0
A18
C2 0.1uF
GND
1
2
C3 0.1uF
C2 & C3 Are Low ESR Ceramic caps.
CRITICAL PCB LAYOUT, See PLX docs.
1.5VCC
PCIE12VCC
R24
0
C11
+
10uF 16V
8311_PLL1.5VCC
TP32
C16
0.1uF
PLACE CLOSE TO 8311!
C18
C19
C20
C21
C22
C23
C24
0.001uF
0.1uF
0.001uF
0.1uF
0.001uF
0.1uF
0.001uF
PLACE CLOSE TO 8311!
C30
C31
C32
C33
C34
C35
C36
0.001uF
0.1uF
0.001uF
0.1uF
0.001uF
0.1uF
0.001uF
PLACE CLOSE TO 8311!
C47
C41
C42
C43
C44
C45
C46
+
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
47uF 10V
B
C
1.5VCC
3.3VCC
R1
8311_1.5V
R2
O
O
8311_3.3V
U1A
D7
VDD3.3
E5
VDD3.3
F5
VDD3.3
B2
WAKEIN#
A18
ROOT_COMPLEX#
PWR_OK
D2
PWR_OK
PLXT1
A3
PLXT1
1K
A10
PLXT2
0
N1
TEST
0
F3
BUNRI
0
D10
PEX83111
BTON
T4
PERR#
PERST_8311#
C3
PERST#
H1
REFCLK+
H2
REFCLK-
J1
PETp0
K2
PETn0
PERp0
G1
PERp0
PERn0
F2
PERn0
WAKEOUT#
D1
WAKEOUT#
PCIE12VCC {5}
NP
U4
LM1085-3.3, TO-263
3
2
VIN
VOUT
C8
C10
C9
10uF 10V
0.01uF
0.1uF
PCIE3.3VCC
JP2
R29
100
1
R30
100
2
R31
100
3
JP3
R32
100
1
2
3
JP4
1
PCIE12VCC
3.3VCC
2
3
JP5
LED5
LED6
1
2
LED
LED
3
R33
R34
1.2K
330
C
D
8311_PLL1.5VCC
PCIE3.3VCC
C1
GPIO0
R4
GPIO0
B1
GPIO1
10K
GPIO1
D3
GPIO2
GPIO2
A1
GPIO3
U2
AT25640
GPIO3
1
CS#
VCC
K3
EECS#
6
EECS#
SCK
HOLD#
L4
EECLK
5
EECLK
SI
SO
L3
EEWRDATA
3
EEWRDATA
WP#
GND
M3
EERDDATA
EERDDATA
E1
BAR0ENB#
BAR0ENB#
A13
TCK
TCK
A11
TMS
TMS
TMS
A14
TDI
TDI
B14
TRST#
C14
TDO
TDO
C15
ITDO
ITDO
V4
SMC
E2
TMC
V3
TMC1
E3
TMC2
R15
R16
R17
R18
R19
R20
1K
1K
1K
1K
1K
1K
PCIE3.3VCC
R25
3.3VCC
NC
PCIE3.3VCC
R26
10K
SW1
R28
3
0
SW PUSHBUTTON
PERST#
4
GPIO0
LED1
LED1
GPIO1
LED
LED2
LED2
LED
LED3
LED3
GPIO2
LED
LED4
LED4
LED
GPIO3
RN1
274
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date:
Date:
Date:
D
E
PCIE3.3VCC
R5
10K
8
7
2
4
1
2
3
4
5
6
J1
JTAG Port
NP - provisional
PCIE3.3VCC
R21
PLXT1
10k
C4
0.01uF
R22
10k
ITDO
BAR0ENB#
R23
0_NP
JP1
PCIE3.3VCC
R27
U5
10K
5
MR#
VCC
1
PERST_8311#
RESET#
2
RST_IN
GND
MAX6306UK29D3-T
Reset Circuit
Holt Integrated Circuits
Holt Integrated Circuits
Holt Integrated Circuits
23351 Madero, Mission Viejo, CA 92691
23351 Madero, Mission Viejo, CA 92691
23351 Madero, Mission Viejo, CA 92691
www.holtic.com
www.holtic.com
www.holtic.com
HI-PCIe_6130, PCIe bus
HI-PCIe_6130, PCIe bus
HI-PCIe_6130, PCIe bus
Document Number
Document Number
Document Number
R ev
R ev
R ev
A
A
A
Thursday, September 19, 2013
Thursday, September 19, 2013
Thursday, September 19, 2013
Sheet
Sheet
Sheet
2
2
2
o f
o f
o f
7
7
7
E
4
3
2
1
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