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Status Inputs
(R only) - 0x2800-0000
BIT
15
FIELD
"A4"
BIT
7
FIELD
N/A
DO
ACTIVE
HI-6130 outputs a high when the BC or RT is processing a 1553 message.
D1
MTPKTRDY
HI-6130 output. Monitor Packet active high when message complete.
D2
READY
HI-6130 output. Set high when the host can configure the device.
D3
WAIT
HI-6130 output. Not used by this design.
D4
/RT1MC8
HI-6130 output. Outputs a pulse when a Mode Code 8 is received.
D5
/RT2MC8
HI-6130 output. Outputs a pulse when a Mode Code 8 is received.
D6
/IRQ (6130)
HI-6130 interrupt output.
D7
N/A
Not defined.
D8
AUTOEN
Set by the SW2 DIP switch 6. Input to HI-6130 for auto initialization from
EEPROM.
D9
"D5"
Not used by connected to a pad on the PCB from "D5" to the CPLD.
D10
SW2-1
DIP SWITCH user defined.
D11
SW2-2
DIP SWITCH user defined.
D12
SW2-3
DIP SWITCH user defined.
D13
SW2-4
DIP SWITCH user defined.
D14
SW2-5
DIP SWITCH user defined.
D15
"A4"
Not used but is connected to a pad from "A4" to the CPLD.
Secondary Output Latches R/W – 0x2C00-0000
BIT
15-D5
FIELD
N/A
RT2LOCK RT2SSF
RESET
N/A
DO
RT1SSF
RT1 Subsystem Fail input.
D1
RT1LOCK
RT1 RT address input lock input.
D2
MTSTOFF
HI-6130 memory test disable. Set low by internal pull-down resistor.
D3
RT2SSF
RT2 Subsystem Fail input.
D4
RT2LOCK
RT2 RT address input lock input.
D5:D15 N/A
Not defined.
AN-6130PCIe
14
13
SW2-5
SW2-4
SW2-3
6
5
IRQ
RT2MC8 RT1MC8
4
3
MTSTOFF RT1LOCK RT1SSF
0
0
HOLT INTEGRATED CIRCUITS
12
11
SW2-2
SW2-1
4
3
2
WAIT
READY
2
1
0
0
9
10
9
"D5"
AUTOEN
1
MTPKTRDY
ACTIVE
0
0
8
0
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