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AN-6130PCIe
The CPLD is a Lattice LCMX01200 256 BGA device and is programmed through a JTAG port on J2. The
Verilog source code listing is included in this document and the actual Verilog source and constraint files
are included in the Lattice "Diamond" tool project included on the CD-ROM. The CPLD block diagram is
shown below. The CPLD has an internal reset and RC clock generator which is used in Verilog design.
Up to 16 wait states can be programmed in the LB timing controlled by the PEX8311 for the HI-6130,
output latches and input buffers in the CPLD. The value of 14 (0xD) is programmed in the LB EEPROM
(U6). At 50MHz the access time is 1+14 or 1/50MHz * 15 = 300ns. This meets the worst case 240ns
timing requirement of the HI-6130 for non-sequential read cycles with 60ns of margin. The LB BLASTn
signal is used by the CPLD to time when to de-assert the CSn, RWn or WRn signals to the HI-6130 and
the internal latches and input buffers. The ADSn signal from the LB is used by the CPLD to start the bus
cycle. A faster access time could have been used for the GPIO but was kept the same to simplify the
design. See the PEX8311 data book for the LB signal descriptions and timings.
A large portion of the CPLD is unused with sufficient room for custom expansion. A Lattice USB
programming cable PN: PN-USBN-2A is required to reprogram the CPLD but is NOT provided by Holt.
This is only needed if the end user wishes to alter the Verilog code and reprogram the CPLD. Using the
Lattice Diamond CPLD development software is beyond the scope of this document but many tutorials
are built into Lattice Diamond software which is available for download from their website. When the
board powers up, only LED10 is On. This is a convenient way to determine if the CPLD has been
programmed.
The next page shows a block diagram of the CPLD
HOLT INTEGRATED CIRCUITS
10
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