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Table Of Contents
1:
Cover Page
2:
PEX8311 PCI Express Bus
3:
PLX8311 Local Bus
4
4:
CPLD JTAG/6130 Inputs
5:
HI-6130
6:
CPLD - POWER
7:
PEX8311 NC Balls
Lattice LCMX1200C3FTN245I
17 x 17 mm
Address decoder
Chip Selects
RD WR Strobes
6130 RD WR Access LED indicators
3
Status and DIP SW inputs
JTAG
32bit, 50 MHz PLX Local Bus
93C56B
u-Wire EEPROM
(Local Bus Config.)
2
AT25640A
(PCIE Config.)
SPI EEPROM
1
A
B
Block Diagram
Holt HI-6130
MIL-STD 1553
BC, RT, MT
Terminals
LCLK
50MHz
Osc.
PEX 8311-AA66BCF
337 BGA 21 X 21 mm
RESET
12V
12V 3.3V
PCI Express X1
Card-Edge Connector
B
C
9 PIN DF CONN.
XFER
XFER
3.3V
Power Regulators
+2.5 V
+1.5 V
12V to 5V
3V3
HI-6130, PEX8311
DC-DC
C
D
Date
Changes
9/19/2013
Rev A
Holt Integrated Circuits
Holt Integrated Circuits
Holt Integrated Circuits
23351 Madero, Mission Viejo, CA 92691
23351 Madero, Mission Viejo, CA 92691
23351 Madero, Mission Viejo, CA 92691
www.holtic.com
www.holtic.com
www.holtic.com
Title
Title
Title
HI-PCIe_6130
HI-PCIe_6130
HI-PCIe_6130
Size
Size
Size
Document Number
Document Number
Document Number
B
B
B
Date:
Date:
Date:
Thursday, September 19, 2013
Thursday, September 19, 2013
Thursday, September 19, 2013
D
E
4
3
2
1
R e v
R e v
R e v
A
A
A
Sheet
Sheet
Sheet
1
1
1
o f
o f
o f
7
7
7
E
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