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HOLT ADK-6130PCIe User Manual

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ADK-6130PCIe User's Guide –
MIL-STD-1553 PCIe Evaluation Card
November 2017
AN-6130PCIe Rev. D
Holt Integrated Circuits

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Summary of Contents for HOLT ADK-6130PCIe

  • Page 1 ADK-6130PCIe User’s Guide – MIL-STD-1553 PCIe Evaluation Card November 2017 AN-6130PCIe Rev. D Holt Integrated Circuits...

  • Page 2: Revision History

    Revise for API demo program changes. Rev. B 03/04/15 Update board photo on page 1. Rev. C 02/02/16 Updates for Holt API 2.x and PLX SDK 7.2. Updates PLX driver links. Update document to new Rev. D 11/02/17 format. Holt Integrated Circuits...
  • Page 3 The two demo projects provided on the included CD-ROM demonstrate the basic features of the HI-6130 and the Holt API software library. The demo card and software can be used as starting point for any new custom design.

  • Page 4: Evaluation Kit Contents

    Schematics and BOM New in this release: • Updated PLX SDK from 7.11 to 7.20. • Holt API library is updated to Rev. 02-1-2. • Holt API Demo updated to Rev. 2.0. • Holt API Demo updated to demonstrate APIs.
  • Page 5 13. A prebuilt Windows 7 compatible executable demo program is included on the CD- ROM in the folder “Holt HI-6130 PCIe Demo”. Copy this folder to the desktop. Confirm the factory default DIP switch settings: (logic-0 is down, logic-1 is up) RT1 address = 3.
  • Page 6 Holt HI-6130 Demo folder (on the desktop). A menu will be displayed showing sets of numbers 1 though x. The Holt card typically appears as the first item #1 with “9056 10b5” [b:xx s:xx f:xx]. Enter “1” and press Enter.
  • Page 7 Two other LEDs flash when the HI-6130 is read or written by the program to provide a visual aid during software development. LED 8 flashes when a read occurs and LED 9 flashes when a write occurs. Press “q” to quit. This is the end of the Quick Start Guide section. Holt Integrated Circuits...
  • Page 8 AN-6130PCIe Hardware The Holt HI-6130 PCIe interface card consists of three main IC components shown below in the Block Diagram. The PEX 8311 is a PCI Express-to-Generic Local Bus bridge and provides the interface between the PCIe slot and the local bus (LB). A programmed CPLD translates the LB signals into CSn, RDn and WRn strobe signals for the HI-6130 timings.
  • Page 9 PC. A full SDK and RDK reference board design including drivers, documentation and demo software is available from PLX. This PLX RDK was used as the basis for the Holt card. An EEPROM (U6) contains configuration data which the PEX8311 latches in at power up to configure the LB for the target hardware base address space, data bus width, and the number of wait states.
  • Page 10 “K3” Not used but brought out to a pad on the PCB from the CPLD. EECOPY HI-6130 EECOPY input. TEST HI-6130 TEST input. Must be set Low for normal operation. See data sheet for Test Mode details. Holt Integrated Circuits...
  • Page 11 RT1 Subsystem Fail input. RT1LOCK RT1 RT address input lock input. MTSTOFF HI-6130 memory test disable. Set low by internal pull-down resistor. RT2SSF RT2 Subsystem Fail input. RT2LOCK RT2 RT address input lock input. D5:D15 N/A Not defined. Holt Integrated Circuits...
  • Page 12 A large portion of the CPLD is unused with sufficient room for custom expansion. A Lattice USB programming cable PN: PN-USBN-2A is required to reprogram the CPLD but is NOT provided by Holt. This is only needed if the end user wishes to alter the Verilog code and reprogram the CPLD. Using the Lattice Diamond CPLD development software is beyond the scope of this document but many tutorials are built into Lattice Diamond software which is available for download from their website.
  • Page 13 AN-6130PCIe CPLD Functional Block Diagram Holt Integrated Circuits...
  • Page 14 Decoder Initialization EECOPY Logic Message TRANSCEIVER Processor VCCP POWER BCENA BCTRI G LOGIC POWER MTENA Discrete RT1ENA Signal Serial Inputs RT2ENA Peripheral ACKIRQ Interface Test TEST (SPI) to Logic RT1SSF MODE EEPROM RT2SSF OPTIONAL SERIAL EEPROM (AUTO-CONFIG) Holt Integrated Circuits...
  • Page 15 PLX SDK installation To modify the demo programs the PLX SDK must first be installed so that the Holt projects can be added to the SDK samples folder. To develop custom software applications for this card, the SDK from PLX is required.
  • Page 16 Follow these steps to install the demo project into the PLX SDK Samples folder: Install the PLX SDK. Locate the zipped Holt demo project “PCIe 6130 Test.zip” on the CD-ROM and unzip this project folder into the Samples folder shown.
  • Page 17 These are not included in the SDK. • Holt HI-6130 data sheet. Provided on the CD-ROM. • Holt high-level API software users manual. Provided on the CD-ROM. Other useful application notes from Holt: • AN-6130_x.pdf •...
  • Page 18 HI-6130 and the inputs are used to read HI-6130 status and DIP switches. The Holt demo code includes several functions to read and write to the HI-6130 memory space, latches and input status buffers. The API functions are located in HI6130.c. These functions use a PLX API to access the LB with either “PlxPci_PciBarSpaceRead(…)”...
  • Page 19 PLX. For detailed information on these parameters and the PLX API’s refer to the PLX SDK user’s guide and data sheet on the PEX8311. For the Holt card, there is no need to alter any of these values.
  • Page 20 Pressing “?” followed by a Return in this window lists a Help page of the commands. The commands are also documented in the PLX API user manual and some examples are provided in the PLX PEX8311 RDK Hardware Reference Manual. Holt Integrated Circuits...
  • Page 21 Output window which can be ignored but there should be no critical errors preventing the debugger from running the project. A menu will be displayed showing sets of numbers 1 though x. The Holt card typically appears as the first item, #1 with “9056 10b5” [b:xx s:xx f:xx]. Enter “1” and press Enter.
  • Page 22 Notice the MSB is high (8) in word address 0x0001, this is the READY bit indicating the HI-6130 is ready for host access. Widen the Tera-Term window enough to view the full 16 registers across for best viewing. Holt Integrated Circuits...
  • Page 23 AN-6130PCIe General structure of demo functions The Holt API demonstration program is contained in module "demos.c". The API libraries are contained in the library file " apiLib.lib " as executable object code. "Demos.c" contains the demo initialization API function calls supporting demonstrations executed from the console menu to initialize the BC, RT(s) and monitor terminals.
  • Page 24 5. From program launch, if the BC is started before enabling the ‘K’ and ‘T’ sequence to display message traffic, the first message may contain an error. This is normal; this occurs because the RT and MT are enabled midstream of a message in progress. Holt Integrated Circuits...
  • Page 25 Bus B. Bus B is used to make it easier to see on the scope. If the RTs were not enabled, retry messages would appear on bus B making it more difficult to see the three inserted messages. This will only work once after a power up or RESET. Holt Integrated Circuits...
  • Page 26 7. BC High priority asynchronous message insertion. Follow the same steps as the previous BC low priority message example but this time Press ‘H’ to insert a single high priority after completion of the current scheduled message. This command is repeatable. Holt Integrated Circuits...
  • Page 27 Press ‘N’ to execute the BC transmissions (15 messages are transmitted) which will appear on the bus as shown below. To optionally see the message traffic on the console, enable the RT message traffic by pressing ‘T’ if it hasn’t already been enabled. Holt Integrated Circuits...
  • Page 28 These demo commands initialize the SMT or IMT monitor features in the HI-6130 and return to the main menu, they do not display any information on the console. The SMT is also initialized and used in the ‘T’ RT Traffic command. Holt Integrated Circuits...
  • Page 29 All messages are transacted properly and captured by enabled RT and MT, some messages simply will not be shown on the console. Holt API function calls are fully described in the Holt API User’s Guide HI-6130-API_xx.pdf included in the ADK CD-ROM.
  • Page 30 AN-6130PCIe Appendix – A CPLD Verilog Source A current copy of this source file is included in the Verilog source file on the CD-ROM. // Holt PCI_6130 interface module count_osc (rstn, osc_clk, LED, clk, // clk and reset pins testpoint,...
  • Page 31 && ~ads) RDn <= 1'b0; // set rd low // generate bracketed WRn stobe always @(posedge lclk or negedge blastq) begin if (~blastq) WRn <= 1'b1 ; // set wr high if blast_q =0 else begin Holt Integrated Circuits...
  • Page 32 Read Input Buffers, or Latches 16 GPIO's ------------*/ always @(*) begin if(~RDn & (add_L==`InputsAddress)) oe=1'b1; // turn on buffer else if(~RDn & (add_L==`LatchAddress)) oe=1'b1; // turn on buffer else if(~RDn & (add_L==`Latch2Address)) oe=1'b1; // turn on buffer Holt Integrated Circuits...
  • Page 33 The c_delay counter is used to slow down the internal oscillator (OSC) output to a rate of approximately 0.5 Hz always @(posedge osc_clk or negedge rstn) begin if (~rstn) c_delay <= 32'h0000 ; else c_delay <= c_delay + 1; assign clk = c_delay[18] ; endmodule Holt Integrated Circuits...
  • Page 34 MIL-STD-1553. ARINC 429 Holt has several ARINC 429 protocol receivers and transmitters that could be interfaced to the PCIe local bus (LB) and CPLD on this design. All the same hardware and software techniques apply. The devices that have a parallel interface would be the easiest to interface on the LB.

  • Page 35: Power Supplies

    PCIe current draw from the 12V rail cannot exceed 0.5A for x1 cards, 2.1A for x4/x8 cards or 4.4A for x16 cards. For a PCIe x1 card (like the Holt example) the worst-case available power from the slot 12V rail is (12V minus 8%) x .5A = 5.52W.

  • Page 36: Additional Memory

    PCB layout considerations The PLX data book and hardware checklist should be closely followed for the PCIe high speed bus signals. Review the Holt AN-550 for PCB layout guidelines for the transformers and decoupling capacitors for the HI-6120, HI-6130 and HI-6140.
  • Page 37 The Holt HI-6130 PCIe low profile card reference design demonstrates how to interface the HI-6130 MIL- STD-1553 multi-terminal to a 1 lane (x1) PCIe bus. A Holt high-level API software library is provided and demonstrated in the demo software. All the design files are included on the CD-ROM, including the OrCAD schematics, two software demo projects and Verilog source for the CPLD with other related documents to enable rapid custom development.

  • Page 38: Block Diagram

    12V to 5V HI-6130, PEX8311 DC-DC 12V 3.3V PCI Express X1 Card-Edge Connector Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com...
  • Page 39 0.1uF 0.001uF 0.1uF 0.001uF 0.1uF 0.001uF 0.1uF 0.001uF GPIO3 Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 10uF 10V 10uF 10V 10uF 10V 8311_1.5V PLACE CLOSE TO 8311! 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 Place one cap.
  • Page 40 0.01uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 0.01uF 10uF 10V 10uF 10V 0.1uF 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com...
  • Page 41 HEADER 10 AUTOEN DIP SWITCHES header_1x2Male pins header_1x2Male pins SMD 6-POS DIP Switch CT2196LPST-ND Default: SW2 position 6 (AUTOEN) Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits www.holtic.com www.holtic.com www.holtic.com should be Open (UP). 23351 Madero, Mission Viejo, CA 92691...
  • Page 42 TERMINAL 1 TERMINAL 2 RT2A3 ADDRESS ADDRESS RT2A4 nECS RT2AP Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits SMD 6-POS DIP Switch SMD 6-POS DIP Switch RT2LOCK 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com...
  • Page 43 NC/PR15A/PR18A/LV_T 4u7 10V PR6B/PR8D/PR10D NC/PR15B/PR18B/LV_C NC/PR16A/PR20A NC/PR16B/PR20B Pin name sequence PR(640,1200,2280) Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com www.holtic.com www.holtic.com...
  • Page 44 PEX83111 Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com www.holtic.com www.holtic.com Title Title Title PEX 8311, NC BALLS PEX 8311, NC BALLS...
  • Page 45 IC EEPROM 512Kbit 20 MHz 8-SOIC 25LC512T-I/SNCT-ND Micro Chip 25LC512T-I/SN IC, EEPROM 64K 20MHz 8-SOIC AT25640B-SSHL-T-ND Atmel AT25640B-SSHL-T IC HI-6130 100-PQFP HI-6130 Holt IC Transformer PM-DB2791S 2.5T T1,T2 PM-DB2791S Holt IC Regulator LDO 1.5V 0.25A SOT23-5 LP2992IM5-1.5/NOPBCT-ND LP2992IM5-1.5/NOPB Regulator 3.3V 3A, DDPAK TO-263-4 LM1085IS-3.3/NOPB-ND...
  • Page 46 Bus A BJ77 Female1 Bus B BJ77 Female DB9M 3 Feet Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com www.holtic.com www.holtic.com...