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HOLT AN-6130PCIe MIL-STD 1553 User Manual

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AN-6130PCIe
MIL-STD 1553 PCIe Card
Evaluation Card Users Guide
March 4, 2015
Introduction:
The Holt HI-6130 PCIe MIL-STD-1553 is a PC interface card designed to interface the Holt HI-6130 MIL-
STD-1553 multi-terminal to a single lane x1, x4/8 or x16 PCI Express (PCIe) 1.1 slot on a PC running
Windows 7. The HI-6130 is a single supply 3.3V rail BC/MT/RT1/RT2 Multi-Terminal device for MIL-STD-
1553 dual redundant bus communications. The card is bundled with the Holt high-level API software
library and two demo programs. The two demo projects provided on the included CD-ROM demonstrate
the basic features of the HI-6130 and the Holt API software library. The demo card and software can be
used as starting point for any new custom design.
HOLT INTEGRATED CIRCUITS
AN-6130PCIe Rev. B
1

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  Summary of Contents for HOLT AN-6130PCIe MIL-STD 1553

  • Page 1 The two demo projects provided on the included CD-ROM demonstrate the basic features of the HI-6130 and the Holt API software library. The demo card and software can be used as starting point for any new custom design.
  • Page 2: Evaluation Kit Contents

    AN-6130PCIe Evaluation Kit Contents • This Application Note, AN-6130PCIe User’s Guide. • Holt API library software and user manual. • ANSI C HI-6130PCIe test demo project. • ANSI C HI-6130 PCIe API demo project. • 9 Pin-D to MIL-STD-1553 BNC breakout cable.
  • Page 3 Holt HI-6130 Demo folder (on the desktop). A menu will be displayed showing sets of numbers 1 though x. The Holt card typically appears as the first item #1 with “9056 10b5” [b:xx s:xx f:xx]. Enter “1” and press Enter.
  • Page 4 Receive command with 32 data words to subaddress SA1 on Bus A, Message 2 is a Transmit command with 32 data words to SA1 on Bus B and Message 3 is a Receive command with 32 data words to SA1 on Bus A. HOLT INTEGRATED CIRCUITS...
  • Page 5 Two other LEDs flash when the HI-6130 is read or written by the program to provide a visual aid during software development. LED 8 flashes when a read occurs and LED 9 flashes when a write occurs. Press “q” to quit. This is the end of the Quick Start Guide section. HOLT INTEGRATED CIRCUITS...
  • Page 6 AN-6130PCIe Hardware The Holt HI-6130 PCIe interface card consists of three main IC components shown below in the Block Diagram. The PEX 8311 is a PCI Express-to-Generic Local Bus bridge and provides the interface between the PCIe slot and the local bus (LB). A CPLD translates the LB signals into CSn, RDn and WRn strobe signals for the HI-6130 timings.
  • Page 7 SDK and RDK reference board design including drivers, documentation and demo software is available from PLX. This PLX RDK was used as the basis for the Holt card. An EEPROM (U6) contains configuration data which the PEX8311 latches in at power up to configure the LB for the target hardware base address space, data bus width, and the number of wait states.
  • Page 8 “K3” Not used but brought out to a pad on the PCB from the CPLD. EECOPY HI-6130 EECOPY input. TEST HI-6130 TEST input. Must be set Low for normal operation. See data sheet for Test Mode details. HOLT INTEGRATED CIRCUITS...
  • Page 9 RT1 Subsystem Fail input. RT1LOCK RT1 RT address input lock input. MTSTOFF HI-6130 memory test disable. Set low by internal pull-down resistor. RT2SSF RT2 Subsystem Fail input. RT2LOCK RT2 RT address input lock input. D5:D15 N/A Not defined. HOLT INTEGRATED CIRCUITS...
  • Page 10 A large portion of the CPLD is unused with sufficient room for custom expansion. A Lattice USB programming cable PN: PN-USBN-2A is required to reprogram the CPLD but is NOT provided by Holt. This is only needed if the end user wishes to alter the Verilog code and reprogram the CPLD. Using the Lattice Diamond CPLD development software is beyond the scope of this document but many tutorials are built into Lattice Diamond software which is available for download from their website.
  • Page 11 AN-6130PCIe CPLD Functional Block Diagram HOLT INTEGRATED CIRCUITS...
  • Page 12 Decoder Initialization EECOPY Logic Message TRANSCEIVER Processor VCCP POWER BCENA BCTRI G LOGIC POWER MTENA Discrete RT1ENA Signal Serial Inputs RT2ENA Peripheral Interface ACKIRQ Test TEST (SPI) to Logic RT1SSF MODE EEPROM RT2SSF OPTIONAL SERIAL EEPROM (AUTO-CONFIG) HOLT INTEGRATED CIRCUITS...
  • Page 13 PLX SDK installation To modify the demo programs the PLX SDK must first be installed so that the Holt projects can be added to the SDK samples folder. To develop custom software applications for this card, the SDK from PLX is required.
  • Page 14 Follow these steps to install the demo project into the PLX SDK Samples folder: Install the PLX SDK. Locate the zipped Holt demo project “PCIe 6130 test.zip” on the CD-ROM and unzip this project folder into the C:\Plx\PlxSdk\Samples folder. Use this directory structure because some PLX files reference other files in these directories.
  • Page 15 PLX PEX8311 RDK Hardware Reference Manual and the PLX PEX8311 data book. Latest versions are available from the PLX website. These are not included in the SDK. • Holt HI-6130 data sheet. Provided on the CD-ROM. • Holt high-level API software users manual. Provided on the CD-ROM. Other useful documents: • AN-6130_x.pdf •...
  • Page 16 HI-6130 and the inputs are used to read HI-6130 status and DIP switches. The Holt demo code includes several functions to read and write to the HI-6130 memory space, latches and input status buffers. The API functions are located in HI6130.c. These functions use a PLX API to access the LB with either “PlxPci_PciBarSpaceRead(…)”...
  • Page 17 AN-6130PCIe Select the Holt PCIe card from the Command menu (or press the green icon button on the left) and select the device with Dev ID = 9056 and Ven ID = 10B5. The PEX8311 consists internally of a PEX8111 and a PCI9056.
  • Page 18 PLX. For detailed information on these parameters and the PLX API’s refer to the PLX SDK user’s guide and data sheet on the PEX8311. For the Holt card, there is no need to alter any of these values.
  • Page 19 Output window which can be ignored but there should be no critical errors preventing the debugger from running the project. A menu will be displayed showing sets of numbers 1 though x. The Holt card typically appears as the first item, #1 with “9056 10b5” [b:xx s:xx f:xx]. Enter “1” and press Enter.
  • Page 20 AN-6130PCIe The main menu will appear below. Press D to display the HI-6130 system registers with labels followed by the same registers values formatted by beginning and end addressed rows followed by eight register values. HOLT INTEGRATED CIRCUITS...
  • Page 21 This waveform shows no RT responding, viewed at the ABUS test point. The ABUS output should be terminated with 70 ohms or the waveforms will appear distorted. The double messages occur because one retry upon message failure is enabled in each BC Message Block. HOLT INTEGRATED CIRCUITS...
  • Page 22 B. The waveform below shows the HI-6130 RT1 responding to BC command with matching address. The bus output should be terminated with 70 ohms and the RT response data shows same amplitude as BC since RT transmission occurs on the same bus stub as BC transmission. HOLT INTEGRATED CIRCUITS...
  • Page 23 RT or not. The source code for these demos is located in the demos.c module of the PCIe6130 Holt Visual Studio project. To learn more about the Holt high-level software API’s and these demos, refer to the Holt API software library user’s guide.
  • Page 24 AN-6130PCIe Console main menu and HI-6130 registers: SRT enabled showing message traffic received using ‘B’ command and ‘N’ command. HOLT INTEGRATED CIRCUITS...
  • Page 25 AN-6130PCIe SRT showing Mode Codes received transmitted from an external BC HOLT INTEGRATED CIRCUITS...
  • Page 26 AN-6130PCIe Appendix – A CPLD Verilog Source A current copy of this source file is included in the Verilog source file on the CD-ROM. // Holt PCI_6130 interface module count_osc (rstn, osc_clk, LED, clk, // clk and reset pins testpoint,...
  • Page 27 && ~ads) RDn <= 1'b0; // set rd low // generate bracketed WRn stobe always @(posedge lclk or negedge blastq) begin if (~blastq) WRn <= 1'b1 ; // set wr high if blast_q =0 else begin HOLT INTEGRATED CIRCUITS...
  • Page 28 Read Input Buffers, or Latches 16 GPIO's ------------*/ always @(*) begin if(~RDn & (add_L==`InputsAddress)) oe=1'b1; // turn on buffer else if(~RDn & (add_L==`LatchAddress)) oe=1'b1; // turn on buffer else if(~RDn & (add_L==`Latch2Address)) oe=1'b1; // turn on buffer HOLT INTEGRATED CIRCUITS...
  • Page 29 The c_delay counter is used to slow down the internal oscillator (OSC) output to a rate of approximately 0.5 Hz always @(posedge osc_clk or negedge rstn) begin if (~rstn) c_delay <= 32'h0000 ; else c_delay <= c_delay + 1; assign clk = c_delay[18] ; endmodule HOLT INTEGRATED CIRCUITS...
  • Page 30 MIL-STD-1553. ARINC 429 Holt has several ARINC 429 protocol receivers and transmitters that could be interfaced to the PCIe local bus (LB) and CPLD on this design. All the same hardware and software techniques would apply. The devices that have a parallel interface would be the easiest to interface on the LB.
  • Page 31: Power Supplies

    PCIe current draw from the 12V rail cannot exceed 0.5A for x1 cards, 2.1A for x4/x8 cards or 4.4A for x16 cards. For a PCIe x1 card (like the Holt example) the worst-case available power from the slot 12V rail is (12V minus 8%) x .5A = 5.52W.
  • Page 32: Additional Memory

    PCB layout considerations The PLX data book and hardware checklist should be closely followed for the PCIe high speed bus signals. Review the Holt AN-550 for PCB layout guidelines for the transformers and decoupling capacitors for the HI-6120, HI-6130 and HI-6140.
  • Page 33 The Holt HI-6130 PCIe low profile card reference design demonstrates how to interface the HI-6130 MIL- STD-1553 multi-terminal to a 1 lane (x1) PCIe bus. A Holt high-level API software library is provided and demonstrated in the demo software. All the design files are included on the CD-ROM, including the Orcad schematics, two software demo projects and Verilog source for the CPLD with other related documents to enable rapid custom development.
  • Page 34: Block Diagram

    12V to 5V HI-6130, PEX8311 DC-DC 12V 3.3V PCI Express X1 Card-Edge Connector Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com...
  • Page 35 0.1uF 0.001uF 0.1uF 0.001uF 0.1uF 0.001uF 0.1uF 0.001uF GPIO3 Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 10uF 10V 10uF 10V 10uF 10V 8311_1.5V PLACE CLOSE TO 8311! 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 Place one cap.
  • Page 36 0.01uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 0.01uF 10uF 10V 10uF 10V 0.1uF 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com...
  • Page 37 HEADER 10 AUTOEN DIP SWITCHES header_1x2Male pins header_1x2Male pins SMD 6-POS DIP Switch CT2196LPST-ND Default: SW2 position 6 (AUTOEN) Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits www.holtic.com www.holtic.com www.holtic.com should be Open (UP). 23351 Madero, Mission Viejo, CA 92691...
  • Page 38 TERMINAL 1 TERMINAL 2 RT2A3 ADDRESS ADDRESS RT2A4 nECS RT2AP Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits SMD 6-POS DIP Switch SMD 6-POS DIP Switch RT2LOCK 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com...
  • Page 39 NC/PR15A/PR18A/LV_T 4u7 10V PR6B/PR8D/PR10D NC/PR15B/PR18B/LV_C NC/PR16A/PR20A NC/PR16B/PR20B Pin name sequence PR(640,1200,2280) Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com www.holtic.com www.holtic.com...
  • Page 40 PEX83111 Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com www.holtic.com www.holtic.com Title Title Title PEX 8311, NC BALLS PEX 8311, NC BALLS...
  • Page 41 Bus A BJ77 Female1 Bus B BJ77 Female DB9M 3 Feet Holt Integrated Circuits Holt Integrated Circuits Holt Integrated Circuits 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 23351 Madero, Mission Viejo, CA 92691 www.holtic.com www.holtic.com www.holtic.com...
  • Page 42 IC EEPROM 512Kbit 20 MHz 8-SOIC 25LC512T-I/SNCT-ND Micro Chip 25LC512T-I/SN IC, EEPROM 64K 20MHz 8-SOIC AT25640B-SSHL-T-ND Atmel AT25640B-SSHL-T IC HI-6130 100-PQFP HI-6130 Holt IC Transformer PM-DB2791S 2.5T T1,T2 PM-DB2791S Holt IC Regulator LDO 1.5V 0.25A SOT23-5 LP2992IM5-1.5/NOPBCT-ND LP2992IM5-1.5/NOPB Regulator 3.3V 3A, DDPAK TO-263-4 LM1085IS-3.3/NOPB-ND...
  • Page 43: Revision History

    REVISION HISTORY Date Description of Change AN-6130PCIe NEW 09/27/2013 Release AN-6130PCIe A 06/30/2014 Revise for API demo program changes. AN-6130PCIe B 03/04/2015 Update board photo on page 1.