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A
U8A
VCCIO0
B2
{5}
ACTIVE
NC/PT2A/PT2C
B3
{5}
MTPKTRDY
NC/PT2B/PT2D
4
A2
{5}
READY
PT2A/PT3A/PT3A
A3
{5}
nWAIT
PT2B/PT3B/PT3B
D3
{5}
RT1MC8n
NC/PT2C/PT3C
D4
{5}
RT2MC8n
NC/PT2D/PT3D
C4
{5}
IRQn
PT2E/PT4A/PT4A
C5
PT2F/PT4B/PT4B
AUTOEN
D6
{5}
AUTOEN
PT2C/PT3C/PT5A
D5
PT2D/PT3D/PT5B
SW1
B4
PT3A/PT3E/PT5C
SW2
B5
PT3B/PT3F/PT5D
SW3
E7
NC/PT4C/PT6E
SW4
E6
NC/PT4D/PT6F
SW5
A5
PT3E/PT5A/PT6C
A4
PT3F/PT5B/PT6D
C6
PT3C/PT5C/PT6A
C7
3
PT3D/PT5D/PT6B
B6
PT4A/PT5E/PT7A
B7
PT4B/PT5F/PT7B
A6
PT4C/PT6A/PT7C
A7
PT4D/PT6B/PT7D
B8
PT4E/PT6C/PT8C
C8
PT4F/PT6D/PT8D
Pin name sequence
PT(640,1200,2280)
I/Os in Bank 0
for XO1200
2
SW1
SW2
SW3
SW4
SW5
AUTOEN
SW2
DIP SWITCHES
SMD 6-POS DIP Switch
CT2196LPST-ND
3V3
1
Default: SW2 position 6 (AUTOEN)
should be Open (UP).
A
B
LCMXO640/1200/2280-FT256/FTN256
pad
1
8
VCCIO1
D7
PT5B/PT6F/PT9B/CLK0
D8
LD0
PT5A/PT6E/PT9A
E8
LD1
PT9A/PT7A/PT9C
E9
LD2
PT9B/PT7B/PT9D
A10
LD3
PT6A/PT7C/PT10A
A9
PT6B/PT7D/PT10B/CLK1
C9
LD4
PT6C/PT7E/PT10C
C10
LD5
PT6D/PT7F/PT10D
D9
LD6
PT8C/PT8A/PT10E
D10
LD7
PT8D/PT8B/PT10F
B9
LD8
PT5C/PT8C/PT11A
B10
LD9
PT5D/PT8D/PT11B
A11
LD10
PT7C/PT8E/PT12A
A12
LD11
PT7D/PT8F/PT12B
B11
LD12
PT7A/PT9A/PT12C
B12
LD13
PT7B/PT9B/PT12D
C11
LD14
PT8A/PT9C/PT13C
C12
LD15
PT8B/PT9D/PT13D
A13
PT7E/PT9E/PT14A
A14
PT7F/PT9F/PT14B
D11
PT9C/PT10A/PT14C
D12
PT9D/PT10B/PT14D
E10
NC/PT10C/PT15A
E11
NC/PT10D/PT15B
B13
PT9E/PT10E/PT15C
C13
PT9F/PT10F/PT15D
B14
NC/PT11A/PT16A
C14
NC/PT11B/PT16B
A15
NC/PT11C/PT16C
B15
NC/PT11D/PT16D
I/Os in Bank 1
for XO2280
GND
TP30
J14
1
1
2
2
header_1x2Male pins
3V3
header_1x2Male pins
B
C
LD[15:0] {3,5}
pad
1
1
JTAG
J2
1
3V3
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
header_1x8 Male pins
FB5
1
2
3V3
FB4
1
2
PCIE12VCC
{2}
HEADER 10
J12
J15
1
1
2
2
C
D
U8C
LCMXO640/1200/2280-FT256/FTN256
VCCIO5
VCCIO4
P2
N8
NC/PB2A/PB2A
PB5A/PB7A/PB10E
P3
N9
NC/PB2B/PB2B
PB5B/PB7B/PB10F/CLK2
N5
P9
NC/PB2C/PB2C
PB7A/PB7C/PB10C
N6
P10
NC/PB2D/PB2D
PB7B/PB7D/PB10D
T2
M10
PB2A/PB3A/PB3A
PB6A/PB7E/PB10A
T3
M9
PB2B/PB3B/PB3B
PB6B/PB7F/PB10B/CLK3
R4
R9
PB2C/PB3C/PB3C
PB6C/PB8A/PB11C
R5
R10
PB2D/PB3D/PB3D
PB6D/PB8B/PB11D
P5
T10
PB3A/PB4A/PB4A
PB7C/PB8C/PB12A
P6
T11
PB3B/PB4B/PB4B
PB7D/PB8D/PB12B
T5
N10
PB3C/PB4C/PB4C
NC/PB8E/PB12C
T4
N11
PB3D/PB4D/PB4D
NC/PB8F/PB12D
R6
R11
PB4A/PB5A/PB5A
PB7E/PB9A/PB13A
T6
R12
PB4B/PB5B/PB5B
PB7F/PB9B/PB13B
T8
P11
PB4C/PB5C/PB6A
PB8A/PB9C/PB13C
T7
P12
PB4D/PB5D/PB6B
PB8B/PB9D/PB13D
M7
T13
NC/PB6A/PB7C
PB8C/PB9E/PB14A
M8
T12
NC/PB6B/PB7D
PB8D/PB9F/PB14B
R7
R13
PB4E/PB6C/PB8C
PB9A/PB10A/PB14C
R8
R14
PB4F/PB6D/PB8D
PB9B/PB10B/PB14D
T14
PB9C/PB10C/PB15A
T15
PB9D/PB10D/PB15B
R3
R15
TCK
NC/PB11A/PB16A
N7
R16
TDI
NC/PB11B/PB16B
M6
TDO
P4
P13
TMS
SLEEPN
P14
PB9F/PB10F/PB15D
P15
NC/PB11C/PB16C
P16
NC/PB11D/PB16D
Pin name sequence
PB(640,1200,2280)
I/Os in Bank 5
I/Os in Bank 4
for XO1200
for XO2280
Holt Integrated Circuits
Holt Integrated Circuits
Holt Integrated Circuits
23351 Madero, Mission Viejo, CA 92691
23351 Madero, Mission Viejo, CA 92691
23351 Madero, Mission Viejo, CA 92691
Title
Title
Title
Size
Size
Size
Document Number
Document Number
Document Number
B
B
B
Date:
Date:
Date:
Thursday, September 19, 2013
Thursday, September 19, 2013
Thursday, September 19, 2013
D
E
pad
1
(rstn)
2
LCLK {3}
3V3 {5,6}
3V3
10K
R57
HEADER 10
T7
T6
3V3
T5
10
T7
9
T3
T6
8
T2
T5
7
T4
6
T3
5
T4
T2
4
T1
3
T1
T0
2
T0
1
J3
Provisonal - Female header
www.holtic.com
www.holtic.com
www.holtic.com
HI-6130 Status Inputs, JTAG
HI-6130 Status Inputs, JTAG
HI-6130 Status Inputs, JTAG
R e v
R e v
R e v
A
A
A
Sheet
Sheet
Sheet
4
4
4
o f
o f
o f
7
7
7
E
4
3
2
1
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