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The PEX8300 is used in "EndPoint" mode which operates in slave mode relative to the host PC. A full
SDK and RDK reference board design including drivers, documentation and demo software is available
from PLX. This PLX RDK was used as the basis for the Holt card. An EEPROM (U6) contains configuration
data which the PEX8311 latches in at power up to configure the LB for the target hardware base address
space, data bus width, and the number of wait states. The data bus width is configured for 16-bits to
match the width of the HI-6130. A second EEPROM is also connected to the PEX8311 for optional
parameters to enable special configurations mainly for the PCIe side. A second EEPROM (U2) is installed
for optional PCIe bus configuration but it may or may not be used. PLX recommends installing this
EEPROM just in case of future needs. These EEPROMs can be examined and programmed using the
PlxMon utility. The PLX utility program "PlxMon.exe" is located in the\Plx\ ...\Bin folder after the SDK is
installed. Information on how to use this utility is located in the PlxSdkUsersManual document in section
4 "PLX Debug Utilities". Holt uses this utility to program the two EEPROMs.
The HI-6130 uses a 16-bit data bus, 16-bit address bus and three more lines to select the device during
reads and writes. The CS0n, WRn and RDn are decoded by the CPLD and routed to the HI-6130. Only the
upper address lines (LA31:LA26) of the LB are decoded by the CPLD for the chip selects. The LB address
and data lines connect directly from the PEX8311 to the HI-6130. In addition to these lines are several
dedicated inputs and outputs listed below going to the HI-6130 from the CPLD. For a complete
description of the HI-6130, refer to the Holt data sheet and application notes that are included on the
CD-ROM.
The functions provided by the CPLD:
•
HI-6130 interface signals CSn, RDn and WRn meeting the HI-6130 timings.
•
HI-6130 write and read access LED's.
•
Output latches with read-back for control signals to the HI-6130 and LEDs.
•
HI-6130 status and DIP switch inputs.
•
Interrupt source pin. The CPLD logically OR's the HI-6130 IRQ, RT1MC8 and RT2MC8 signals into
a single signal that is connected to the interrupt pin of the PLX8311. See the software section for
information how PLX API's handles interrupts. PLX includes a demo project "LocalToPciInt" to
demonstrate how interrupts are handled. The technique used in "LocalToPciInt" was used in the
Holt demos.
AN-6130PCIe
HOLT INTEGRATED CIRCUITS
7
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