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AN-6130PCIe
Customization
This section provides guidelines how to enhance the design. This would most likely require a new board
design but limited prototyping could be achieved on a small add-on board, using the fourteen CPLD I/O's
on J12 and J3 header connectors. PCIe12V, 3V3 voltages and ground connections are provided on these
connectors. When adding circuits using these connections, power supply adequacy should be carefully
reevaluated especially when using MIL-STD-1553.
ARINC 429
Holt has several ARINC 429 protocol receivers and transmitters that could be interfaced to the PCIe local
bus (LB) and CPLD on this design. All the same hardware and software techniques would apply. The
devices that have a parallel interface would be the easiest to interface on the LB. Some suggested ARINC
429 16-bit parallel parts are the HI-3582A, HI-3583A and the HI-3584A. For a 3.3V only solution, use the
HI-3584A with a 3.3V single supply rail line driver such as the HI-8596 or the HI-8597 (which includes
built-in Level 3 lightning protection).
The following block diagram shows an interface for two ARINC 429 receivers and one transmitter
powered by a single 3.3V supply meeting DO-160 Level 3 lightning protection. The 1MHz CLK input to
the HI-3584A can be supplied directly by the CPLD or optionally by an external oscillator module. Refer
to the HI-3584A, HI-8597 data sheets and AN-3582A application note for more information on these
ARINC 429 devices. Contact Holt sales for other recommendations.
HOLT INTEGRATED CIRCUITS
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