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AN-6130PCIe
For new custom designs, the user should be aware of the PCIe limitations on the maximum allowable
current and power dissipation, which vary depending on card size (full height vs. low profile) and slot
type used (x1 through x16).
Clocks
A single 50MHz oscillator module is shared between the PEX8311 LB, CPLD and HI-6130. The LB can be
clocked up to 66MHz to achieve faster bus performance which might be desirable in a more complex
design. The HI-6130 must always be clocked at 50MHz so an additional oscillator would be needed. If
running the LB at 66MHz the number of wait states in the PLX LB EPROM registers would need to be
increased to compensate for the faster clock. The LB and the CPLD must use the same clock to generate
the synchronized strobe signals internal to the CPLD and the CSn, RDn and WRn strobe signals to the HI-
6130. For a faster LB, use up to 66MHz for the LB clock input of the PEX8311 and CPLD and use a
separate 50MHz clock for the HI-6130.
Additional memory
Adding additional on-board memory is possible with some moderate design effort. Connect the address
and data bus directly to the LB signals of the PEX8311 and assign the required number of control signals
for the memory by using some spare CPLD pins and modify the Verilog accordingly. Configure the LB
EEPROM Space registers for the desired memory space, number of wait state and bus width type.
PCB layout considerations
The PLX data book and hardware checklist should be closely followed for the PCIe high speed bus
signals. Review the Holt AN-550 for PCB layout guidelines for the transformers and decoupling
capacitors for the HI-6120, HI-6130 and HI-6140.
HOLT INTEGRATED CIRCUITS
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