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i3 2 5 I
CLK
IJSR
III R
8251
CTS
chip address [ 0OOl/xxxx)
Rl
S
TXD
TXRDY
I;\' } #1 X
TXE
OUT
TXC
RXD
RXRDY
RXC
SYN/BD
8253
CLKO
GATEO
8253
OUTO
chip address[OO10/xxxx)
CLK!
GATE!
IN
#}
2XH
OUTl
OUT
#
CLK2
GATE2
OUT2
INTO TO MAIN FROM SUB
POWER ON RESET
SOO 'SIW( IORQ·WR
of
SUB)
INTR=L(FROM MAIN)
INT TO SUB FROM KEY
STK= (L)
IN
IN
OUT
IN
OUT
OUT
:"J.C.
N.C.
IN
IN
OUT
IN
N.C.
IN
IN
OUT
IN
IN
OUT
IN
IN
OUT
2.45MHz clock
DATA SET READY
DATA TERMINAL READY
CLEAR TO SEND
REQUEST TO SEND
TRANSMITTER DATA
TRANSMITTER CLOCK
RECEIVE DATA
RECEIVER READY
RECEIVE CLOCK
2.45MHz
Vcc
To TXC. RXC of the 8251
2.45MHz
From OUT2
MUSIC
2.45MHz
Vcc
To GATE 1
INTO
H
L
H
- 1 / -
READY
CS
.~
MZ 3500
PO (MPER
SUT).
ER
CD
RD
OUT 0 of 8253
SD
To
3
1
ilrCPU 0f l'W'
8253 OUT
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