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MAIN CPU
I/O PORT IN MEMORY MAPPER
ADDRESS
·\7 (AS (AS!A4 (A3(A2(AI (AO
HEX DBIJS
10
DI
~ROH
I
I
I
I
I
I
0
0
FC
-
OUT
DO
I I
D7
~
\{ I '-,
-
I
I
I
I
I
I
0
I
FD
01
M'-.I
--vo
M'-.O
1>7
M>\3
'VG
\lA2
f - - -
DS
M
1\
I
'D4
OUT
MAO
-
D2
M02
---r>l
MOl
1
1
1
I
1
1
1
0
FE
--00
MOO
D4
S\\ 4
-
D3
~
\\ 3
-
D2
IN
~
\\ 2
-
1 - - - -
Dl
~\\]
-
DO
'-,r_L
D7
FU3
' - - -
D6
FD2
-
~
l-
j))
1
1 1 1
I
1
I
I
FF
D4
IN
SRIW
r - - -
D3
SACK
r - - -
D2
11'1'2
I - - -
01
I)\J»
I - - -
DO
I:-':J>O
D7
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F2
r -
OUT
D6
MI, I
1. All output signals are reset to low level upon power on,
except for SRBQ that goes high.
2. Noted with a star mark
"-er"
are input/output signals, and
rest of others are processed in the lSI.
#1 I/O port output of MEl and ME2 uses the memory at
the addresses.
{
ME2
-->
8000"'" BFFF
ME1
-->
4000 ..... 7FFF
When MEl and ME2 are in high state. RSAB (RASA)
IS
inhibited during memory addresses in RAM-A that
correspond to overlayed addresses for ME 1 and M E2
This is not true during SDl mode.
-
M l3;,OO
SRO Bus request from the marn CPU
to
the sub-CPU
Sub-CPU reset SIgnal
J
Memory system define
l
B.o, ",,,, "BO""
m'mo",
.~.
0'
cooo-mF.
I
~
J
Bank select signal to memory area of 2000-3F F F.
\1\1
,
Sub-CPU READY srgnal
Sub-CPU acknowledge signal
I nterrupt status
#-1
J"I'o,e "HI
t
f
Wart timing generator
(SW8\
WAIT
IS
rssued once per main CPU fetch eyele.
Its outut rs tll state
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