Table of Contents
Advertisement
-
M Z3500
4-7. GDC (Graphic display controller) (UPD7220) signal description
Polarity
I
Pin No.
IN/OUT
Function
Signal Name
--
-
- - - - - - - - - - - - - -
-
---
---
~---
-------------
1
2XCCLK
IN
Double character
cloc~
supplied from the external dot timing generator which has t"e followlc,o
I
two modes:
1. Character display mode' Single phase clock at
one
half of the
one
character Wide cycle
2. G'arh,c dlsplav mode:
SI~gle
phase clock of eight dots that cycles
I
-----
-_._
..
_-
----
-
- - - - -
-
-----~
-
--------
0 _
------
--
- -
..
o .
0
\
2
DBIN
OUT
M~mory
contre· Signal
supp'led
to the
Image
memory from the
GOC,
which causes the
Image
memory uutput data to
be
sent on the data bus.
------~
-------- -- --------
3
HSYNC·REF
OUT
Memory contro' signal sent to the image memory from the GDC. which is the horizontal
synchronizing SignaL
• Stnce the image drawing process is automatically interrupted In the dynamic RAM mode the refresh
address is output during the HSYNC period, It can also be used as the refresh timing signal.
• Refresh is accomplished by suppressing the CAS signal derived from the RAS Signal in the external
circuit when the HSYC IS at high lebel (Horizontal Synchronous - Refresh timing)
----
4
VSYNC
IN/OUT
Establishes one of follOWing twO modes. depending on whether the GDC is operated by the master
EX.SY
or the slave.
NC
1.
When the master is operational: sends out the vertical synchronizing signal.
2. When the slave is operational: The synchronizing signal generation counter is initialized by a high
level input.
. -
5
BLNK
OUT
Erase signal output is issued at the following times (blanking signall:
1, Horizontal flyback period,
2. Vertical flyback period
3.
Period from the execution of the SYNC SET command to the execution of the DISP START
command.
6
RAS
OUT
Memory control Signal sent to the Image memory from the GDC,
• In the dynamiC RAM mode.
It
IS
used as the reference signal of RAS, When at high level, used
as the timing Signal by which the address Signal is latched,
(Row Address Strobe)
7
DRO
OUT
DMA request output which is connected with the DRO input of the DMA controller is output by the
(NO USE)
following two commands'
1.
DREOE (DMA request write): CPU memory to image memory,
2, DREOR (DMA request read). Image memory to CPU memory.
It will be continuously output until the DMA transfer word/byte number set by the VECTW (vector
write) command becomes zero.
(DMA Request)
8
DACK
IN
Signal supplied from the DMA controller that is subsequently decoded by the GDC as the read or
(NO USE)
write signal dUring DMA,
(DMA Acknowledge)
9
RD
IN
In the external circuit RD
IS
combined With the chlr select signal (CS). And is used when the CPU
reads from the GDC either data or status flag and the signal DACK,
(Read strobe)
- -
10
WR
IN
In the external ctrcuit WR
IS
combined With the chip select signal. And is used when the CPU
writes to the GDC either a command or parameter and the Signal DACK.
(Write strobe)
0 _ _ _ _ •
11
AO
IN
Normally. connected With the address lme and
1$
uc,ed
TO
deSIgnate data type.
AO
RD
WR
t=unctlon
Device number of
the Model
3500
0
0
1
READ STATUS FLAG
IN
,no
IN
#60
1
0
1
READ DATA
IN
#71
IN
#61
0
1
0
WRITE PARAMETER
OUT
#70
OUT
#60
1
1
0
WRITE COMMAND
OUT
#71
OUT
#61
GDCl
GDC2
(Address Bus 0)
12-19
DBO-DB7
IN/OUT
Bidtrectional data bus connected to the system bus.
(Data Bus 0 - 71
20
GND
IN
OV supply.
21
LPEN
IN
Light pen strobe Input. When a Input light
IS
sensed by the light pen. it outputs a high level Signal.
The CPU can then read the display address via the LPENR (Light Pen Read) command.
O
_ _ _ _
~
_ _
---- -- -----
22-34
ADO-AD12
IN/OUT
B,d"ect,onal address/data bus connected between the Image memory and the GDC on which address
and data are sent on the bus by means of multiplexer ALE (Address Latch Enable)
IS
drlved from
the RAS output
In
the external
CirCUIt.
(Address(Da13 bus 0 - 12)
Advertisement
Table of Contents
