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M Z3500
Operattonal description
(1) Upon reset after power on, the main CPU loads the
contents of the initial program loader (IPL) into RAM
starting at address 4000H, during which time reset is
applied to the sub·CPU.
TIMING OF RESET SIGNAL
Vee
SYSRES·l.j
. ,
I
1-
I
I
..... - - - - - /
SRES
I
I
I
I
I
+
~
I
I
I
I
I
of
POWER'SUB CPU
I START
POWER
OFF
I
I
MAIN
CPU
START
Memory Map Data:
1.
ROM·B is tested to determine if ROM's are present.
2.
The ROM·IPL functions under control of the main CPU
at first, but later it functions under the sub-CPU after
the IPL program has been loaded in RAM.
3. RAM·COM is shared by both the main CPU and the sub-
CPU.
INITIALIZE FLOW
START
Lwd ... 800TSTRAP
""' -
~"A~ll
~TART
l l ' \4
.... JAf< I
T....wf.r control to
the BOOTSTRAP
Tf1II'\'Ifef'SUB-CPU
sv.-..rr
Pf"ograt'n
to
lh~
sus-CPU
}-
'11.) ........ , ,I<"
-8-
(2) The main CPU then terminates resetting the sub CPU
and starts the sub·CPU. At the same time, the ROM
IPL is assigned to the sub·CPU.
(3) The main CPU then send the memory allocation (state)
to SD1, and starts to load DOS from the system floppy
disk.
Signal generated from the
CR network and power supply
Output Signal from the main
CPu
port
8.
Main
CPU
reset time
b. Main
CPU IPL
load tIme
4.
Memories other than described above cannot be accessed
under the SDO state.
5.
Bank select, MAD-MA3, is used Within the address range
of COOOH-FFFFH.
EAROR
" i l i A ! III
"NlI
.... 1-/1( , ........ , \k J
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