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Polaflty
Pin No.
IN/OUT
Signal Name
32
RF1B
OUT
33
RF2B
OUT
34
WATB
OUT
35
RCMB
OUT
36
ITFB
IN
37
!TOB
IN
38
InB
-
-
IN
39
IT2B
40
MRQB
IN
41
WRB
IN
42
IT3B
-
-
IN
43
IT4B
44
SEC
IN
45
GNO
IN
46
Vcc
IN
47
SW1
-
-
IN
48
SW2
49
AO
IN
50
RFSH
IN
51
SW3
-
-
IN
52
SW4
53
GNO
IN
54
F01
IN
55
Vcc
IN
56
F02
IN
Function
MalO CPU 128KB dynamic RAM output buffer (LS244) output enable signal.
(RAM buffer 1)
Signal Identical to R F 1 B
For option RAM
(RAM buffer 2)
Wait Signal
to
the main CPU
-
M Z 3S00
(One wait cycle 's applied dUring the memory fetch cycle of the main CPU. It consists of one clock
period)
(WAIT)
Chip select Signal Issued from the malO CPU to select the RAM shared by the main CPU and
the sub-CPU
(RAM Common'
Interrupt input from the UP0765 FOC (Floppy Disk Controller).
(Interrupt from Floppy'
Interrupt Input from the sub-CPU.
11
nterrupt from No. 0)
Interrupt Input from slot 1 or 2.
(I nterrupt from No. 1, 2'
Memory request signal from the main CPU.
(Memory Request)
Write Signal from the maon CPU.
(Write)
Interrupt Input from slot 3 or 4.
(I nterrupt from No. 3, 4)
Input from the FOO (Floppy Disk Drive) assignment dip switch (A), '110.1.
·See the dip sw,tch deSCription, provided separately.
(Section)
Ground
5V supply
Input from the s,stem aSSignment dip sWitch.
'See the dip sWitch deSCription, provided separately.
MalO CPU address bus
Used
10
the I/O port select logic in the MMR to designate device number.
Refresh signal from the main CPU.
(Refresh)
I nput from the system assignment dip switch.
·See the dip sWitch description, provided separately.
Ground
Input from the system aSSIgnment dip switch.
'See the dip swotch deSCription, provided separately.
5V supply.
Input from the FOO aSSignment dip sWitch (A), No. 2.
'See the dip sw'·ch deSCription, provided separately.
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I
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