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6-6. 8253
Controls
Baud rate of this interface will be determined by the clock
output of the 8253. The 8251 is configured such that Its
baud rate is 1/16 of the input clock and has the following
relation between the 8253 output clock and the baud rate:
8253 input frequency: 2457.6kHz
8253 Mode set: Mode 3(rec'angle waveform rate generator)
Control signals
Signal name
Symbol
IN/OUT
Baud rate
8253
Output frequency
I 10
:t-
1760Hz
300
4800
600
9600
1200
19200
2400
38400
4800
76800
9600
153600
Function
Transmission enabled
CS
- Peripheral
When high, data input from a peripheral is enabled.
When low, data input from a peripheral is disabled.
Data set ready
OR
- Peripheral
Goes high when power is on to the interface unit.
~
MZ 3500
8253
Parameter
1396.36
512
256
128
64
32
16
Carrier detect
CD
- Peripheral
(SW6-0N) High at all times when power is on to the interface unit.
(SW6-0FF) Goes high only when data is on output.
Ready
READY
- Peripheral
Data output from the interface is enabled.
(ON) Data is output from the interface.
(OF F) WaItS for data output.
NOTE: A maximum of two bytes are output after the signal goes from high to low
state.
Equipment ready
ER
- Peripheral
I ndicates that the peripheral is ready. I t results in an error if low or open when data
is sent from the interface. This signal will be invalidated when the SW5 is turned
off.
Paper out
PO
- Peripheral
(SW7·0N) Causes an error if set high during data output.
(SW7·0F F) Causes an error if set low during data output.
6-7. Description of LSI's
1) UPD8251AC (Programmable Communication Interface)
The UPD8251A is a USART (Universal Synchronous/
Asynchronous Receiver/Transmitter that was specifical-
ly designed for data communication.
The USART receives parallel data from the CPU and
converts it into serial data before transmitting. Also.
serial data is received from an external circuit and trans-
ferred to the CPU after converting it into parallel. The
CPU can monitor the current state of the USART at
any time (data transfer error, and control Signal of
, SYNDET and TXEMPTY.
,-eatures
•
8080A/8085A compatible
•
Synchronous/asychronous operation
•
Synchronous operation
5 - 8 bits character
Clock rate: baud rate xl, x16, x64
BREAK character generation
Stop bit: 1, 1_5,2 bits
Error start bit detection
Automatic break detection and operation_
•
Baud rate: DC - 64K baud
Pin configuration (Top View)
D2
D3
RXD
GND
D4
D5
D6
D7
TXC
\\ R
cs
CoD
RD
RXRDY
D7-DO
1
~
"-
2
~
3
v
4"-
,..
-
5
6
~
"-
7
-
'"
8
-
...
9 ..
v
le!
~
11
r
'"
,..
12
13
O"L
14
Block diagram
28
~
~27
r~
~26
-
--""
-
h.25
1'>.
~
24
f'o.
['-' 23
r;:
I'"'
22
~
21
1'0
~20
-
~
19
"
1 B
r;:
17
r;::
16
15
"
Dl
DO
VCC
RXC
DTR
RTS
DSR
RESET
CLK
TXD
TXEMPTY
crs
SYNDET
TXRDY
TXJ;ul
pc.;..-~rrXE
•
Full-duplex
Double buffer type transmitter/receiver
RESET
ClK
CD
1ITi
I'.R
!====!o.t-~XC
•
Error detect
Parity, overrun, framing
•
Input/output TTL compatible
•
N-channel MOS
•
Single +5V supply
•
Single phase TTL level clock
•
28-pin, plastic DIP
•
Intel8251A compatible
- 75-
l;,
o------T
j);,R
Ti'fk
~
~
Internal data bus
RXll
I
BD
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