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-
\ 1Z3500
4-9. VSYNC
o
40 Digit
From
1 80 Digit
(8255 P87) CH48 - - - - - - - - - ,
Lilt
1
v . . . . .
..,'t
1->.. .....
'r1\l.
L'I'-2
0816
o
~
I
t;
X!>\
t
'"
Jrd
If>llll
""nl
[l
oH-----1
O. BblVwnrd
1.16dlt/\\nrd
80 digit, 16blt/word
Master
IS
GDC-2
2LK2~--'
__
-------------~--4
[Circuit description]
When more than two UPD7220 GDC's are to
be
operated in
parallel, one must be assigned to the master and the other
to the slave in order to mantain synchronous display
timing. The master and the slave are determined according
to the table below. The above circuit shoud be used to
compare with the table description.
~S::::)
CH48
=
0 40 digit CH48 = 1 80 digit
GDC-2 (graphic)
Without VRAM PW8
G DCl (character)
GDC 1
is the master.
8-blt structure [0816=01
GDCl
GDCl
(48K8, 200 raster)
16-blt structure [0816=11
GDCl
GDC2 (Graphic)
(48 96K 8,400 rasters)
The master GDC must be set as indicated above.
[Oprational example]
If It was set to 80 digit, 16 bit/word mode SRES will be
o
when CH48
=
1, 0816
=
1 when not in the reset condi·
tion. These signals are supplied to terminal A (weight 1),
B (weight 2), and G (gate), and set terminal Y3 of the
decoder IC LS139 to "0", so that the YSYNC output of
the GDC2
IS
Input to terminal EX SYNC of the GDC2.
- 46-
o
Set
Reset
SRES (From MMR)
40 digit, 16bll/word
80 digit,
8bll/word
Master
IS
GDC 1
40 digit. 8bll
1
word
Master
IS
GDC 1
Il,k-----.J
2
l L
j
k
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