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M Z 3500
3-5. Memory (ROMIPL, RAMCOM, S-RAM) select circuit
To main CPU
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1) ROM-IPL select by the main CPU
As ROM IPL turns to low level after power on address
bus buffers (LS244, LS367) and data bus buffer
(LS245) are enabled. S of the data selector IC (LS157)
is set to a low level to enable input 1 A-4A. The 3Y and
2Y outputs of the LS157 then go low so that CE and OE
of the ROM-IPL are from main CPU. The contents of
the IPL-ROM are then read by the main CPU. Because
the input pin
(H16)
of the address buffer (LS367) is
connected to Vcc, IPL for the main CPU will be at
address 1000 of the IPL·ROM. Switch SW2BA is the
operation test dip switch which should be ON at all
times.
2) RAM-COM select by the main CPU
When RAM COM is low, SRES high, and SACK low, the
select input S of the selector IC (lS157) is in low state
so that input 1 A-4A becomes effective. That is, the out-
put 4 Y is low and either 1 Y (WE) or 2Y (OE) becomes
low level, so as to enable to read or write RAM-COM.
3) ROM-IPL select by sub-CPU
Normally, the select signal S of the selector is pulled up
to Vcc level that inputs 1B-4B are enabled by sub CPU_
I f A 13 th ru A 15 were to be at low level, the output YO
of the LS139 becomes low level so that the output 3Y
of the LS147 or
CE
of the ROM-IPL should be at low
level. Should SRD, SMRO be at low lebel as well, the
output 2Y of the LS157 or OE of the ROM-IPL turnde
to low lebel to read the ROM-IPL. Though the sub-CPU
can access an address range of 0000 to 1 F FF theoretIcal-
Iy, it would be from 0000 to OF F F, actually.
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4) RAM-COM select by sub-CPU
Y1 of the LS139 changes to low level when AS13 is high
and AS14 and AS15 are low. In other words, the ,"put
4B of the LS157 IS at low level which brings the output
Y4 to low level, so that CS of the RAM-COM chip select
signal should become effective.
If SMRO, SRD or SMRO, SWR is in low level at this
point, it enables read (OE) or write (WE). Address range,
however, is 2000 to 3 F F F
5) RAM (SA, SB, SC, SO) select by sub-CPU
SMRO, SRO (OE) or SMRO, SWR (WE) is at low level
to select the sub-CPU dedicated RAM, SA-SD. Tne
following chip select signal, then becomes valid under
these conditions:
RAMSA
AS11, AS12, AS13, AS14, AS15
(address 4000-47FF)
RAMSB
RAMSC
RAMSD
AS11, AS12, AS13, AS14, AS15
(address 4800-4 F F F)
AS11, AS12, AS13, AS14, AS15
(address 5000-57FF)
AS11,AS12. AS13. AS14,AS15
(address 5800-5 FF F)
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