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10.
THREE-STATE CONTROL: (TSC)
11.
ADDRESS BUS (AO/A15):
12.
DATA BUS (DO/D7):
available. This will occur if the GO/HALT line is in the
Halt (low) mode or the 14PU is in a "Wait" state as the
result of some instruction, such as the WAI instruction.
This input causes all of the address lines and the
Read/Write line to go into the off or high impedance state.
The Valid Memory address and Bus Available signals will be
forced low. The data bus is not affected by TSC and has its
own enable (Data Bus Enable). In DMA applications, the
Three-State Control line should be brought high on the
leading edge of the Phase One Clock. The 11 clock must be
held in the high state for this function to operate
properly. The address bus will then be available for other
devices to directly address memory. Since the MPU is a
dynamic device, it must be refreshed periodically or
destruction of data will occur.
Sixteen pins are used for the address bus. The outputs are
three-state bus drivers capable of driving one standard TTL
load and 130pf at 1 Megahertz.
When the output is turned off, it is essentially an open
circuit. This permits the MPU to be used in DMA
applications.
Eight pins are used for the data bus. It is bi-directional,
transferring data to and from the memory and peripheral
devices. It also has three-state output buffers capable of
driving one standard TTL load and 130pf at 1 Megahertz.
MPU-11
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