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8. Go/Halt(G/H):
9. BUS AVAILABLE (BA):
Request signal, the processor will complete the current
instruction that is being executed before it recognizes the
NMI signal. The interrupt mask bit in the Condition Code
Register has no effect on NMI. The Index Register, Program
Counter, Accumulators, and Condition Code Register are
stored away on the stack. At the end of the cycle, a 16-bit
address will be loaded that points to a vectoring address
which is located in memory locations n-2 and n-3. An
address loaded at these locations causes the MPU to branch
to an nonmaskable interrupt routine in memory.
When this input is in the high state, the machine will
fetch the instruction addressed by the program counter and
start execution. When low all activity in the machine will
be halted. This input is level sensitive. In the halt mode,
the machine will stop at the end of an instruction. Bus
Available will be at a logic "1" level. Valid Memory
Address will be at a logic "0" and all other three-state
lines will be in the three-state mode.
The halt line must go low with the leading edge of phase
one to insure single instruction operation. If the halt
line does not go low with the leading edge of phase one,
one or two instruction operations may result, depending on
when the halt line goes low relative to the phasing of the
clock.
The Bus Available signal will normally be in the low state.
When activated, it will go to the high state indicating
that the MPU has stopped and that the address bus is
MPU-10
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