Overview; Status Byte And Srq; Status Register Sets; Queues - Keithley 2303 User Manual

7-2

Status Structure

Overview

The power supply provides a series of status registers and queues allowing the operator to mon-
itor and manipulate the various instrument events. The status structure is shown in Figure 7-1. The
heart of the status structure is the status byte register. This register can be read by the users test pro-
gram to determine if a service request (SRQ) has occurred, and what event caused it.

Status byte and SRQ

The status byte register receives the summary bits of four status register sets and two queues.
The register sets and queues monitor the various instrument events. When an enabled event
occurs, it sets a summary bit in the status byte register. When a summary bit of the status byte is
set and its corresponding enable bit is set (as programmed by the user), the RQS/MSS bit will
set to indicate that an SRQ has occurred.

Status register sets

A typical status register set is made up of a condition register, an event register and an event
enable register. A condition register is a read-only register that constantly updates to reflect the
present operating conditions of the instrument.
When an event occurs, the appropriate event register bit sets to 1. The bit remains latched to
1 until the register is reset. When an event register bit is set and its corresponding enable bit is
set (as programmed by the user), the output (summary) of the register will set to 1, which in turn
sets the summary bit of the status byte register.

Queues

The power supply uses an output queue and an error queue. The response messages to query
commands are placed in the output queue. As various programming errors and status messages
occur, they are placed in the error queue. When a queue contains data, it sets the appropriate
summary bit of the status byte register.