Platen Gap Motor Drive Circuit - Epson DFX-8500 Service Manual

PLATEN GAP MOTOR DRIVE CIRCUIT

Figure 2-25 shows a block diagram of the platen gap motor drive circuit, and Table 2-11 provides platen gap
motor specifications.
The platen gap motor is a stepping motor. The motor phase switching signals are output from the gate array
ports PGA to PGD. The motor common voltage (PGCOM) alternates between drive mode (+37 VDC) and
hold mode (+5 VDC), according to the PG H/R signal of the gate array. The phase driver circuit is made of
discrete transistors Q12 to Q15.
The phase A output pulse from the platen gap encoder (ENCA) is input to port ENCA on the gate array and
the phase B output pulse from the platen gap encoder (ENCB) is input to port ENCB on the gate array. The
gate array counts these pulses using an internal counter and determines the amount and direction of motor
rotation.
Specification
Form
Supply Voltage
Internal Coil Resistance
Current Consumption
Frequency
Driving Method
Table 2-11. Platen Gap Motor Specifications
Description
4-phase, 48-pole, PM pulse motor
37 VDC (applied to the drive circuit)
250 + 18 Ω per phase at 25
Driving: 0.20 A (average)
Holding: 0.02 A + 5 mA
285 pps
Constant voltage driving, 2-2 phase drive
OPERATING PRINCIPLES
o
C
2-35